参数资料
型号: MCZ33991EGR2
厂商: Freescale Semiconductor
文件页数: 10/36页
文件大小: 0K
描述: IC GAUGE DRIVER SPI 24-SOIC
标准包装: 1,000
应用: 步进电机驱动器,2 相
输出数: 2
电流 - 输出: 100mA
电源电压: 6.5 V ~ 26 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
(Characteristics noted under conditions 4.75 V < V DD < 5.25 V, -40°C < T J < 150°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
SPI TIMING INTERFACE
Recommended Frequency of SPI Operation
f SPI
1.0
3.0
MHz
Falling edge of CS to Rising Edge of SCLK (Required Setup
Time) (15)
T LEAD
50
167
ns
Falling edge of SCLK to Rising Edge of CS (Required Setup Time)
T LAG
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
TS LSU
25
83
ns
Falling Edge of SCLK to SI (Required Hold Time)
SO Rise Time (CL=200pF)
SO Fall Time (CL=200pF)
TSI (HOLD)
Tr SO
Tf SO
25
25
25
83
50
50
ns
ns
ns
SI, CS, SCLK, Incoming Signal Rise Time
Tr SI
50
ns
SI, CS, SCLK, Incoming Signal Fall Time
Tf SI
50
ns
Falling Edge of RST to Rising Edge of RST (Required Setup
Time) (15)
Tw RST
3.0
μ s
14.
Rising Edge of CS to Falling Edge of CS (Required Setup
Time) (15) (20)
T CS
5.0
μ s
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (15)
T EN
5.0
μ s
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
T SO(EN)
T SO(DIS)
1.3
145
4.0
ns
μ s
Time from Rising Edge of SCLK to SO Data Valid
0.2 V DD < = SO> = 0.8 V DD , CL = 200 pF
T VALID
65
105
ns
Notes
15. The maximum setup time that is specified for the 33991 is the minimum time needed from the micro controller to guarantee correct
operation.
16. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
17. Time required for output status data to be available for use at SO. 1 K Ohm load on SO
18. Time required for output status data to be terminated at SO. 1 K Ohm load on SO.
19. Time required to obtain valid data out from SO following the rise of SCLK.
20. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.
The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing , over the temperature range
specified in the environmental requirements section. Digital Interface timing is based on a symmetrical 50% duty cycle SCLK
Clock Period of 333 ns. The device shall be fully functional for slower clock speeds.
33991
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
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