参数资料
型号: MCZ33991EGR2
厂商: Freescale Semiconductor
文件页数: 24/36页
文件大小: 0K
描述: IC GAUGE DRIVER SPI 24-SOIC
标准包装: 1,000
应用: 步进电机驱动器,2 相
输出数: 2
电流 - 输出: 100mA
电源电压: 6.5 V ~ 26 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
TIMING DESCRIPTIONS AND DIAGRAMS
DEVICE FUNCTIONAL DESCRIPTION
Table 17. Velocity Ramp (continued)
Velocity
Position
64
65
66
67
68
69
70
71
Time Between
Steps ( μ s)
385
382
379
376
374
371
368
366
Velocity
( μ Steps/s)
2611.30
2631.90
2652.34
2672.62
2692.75
2712.73
2732.56
2752.25
Velocity
Position
136
137
138
139
140
141
142
143
Time Between
Steps ( μ s)
263
262
261
260
259
258
257
256
Velocity
( μ Steps/s)
3820.33
3834.44
3848.49
3862.50
3876.45
3890.36
3904.22
3918.02
Velocity
Position
208
209
210
211
212
213
214
215
Time Between
Steps ( μ s)
212
212
211
211
210
210
209
209
Velocity
( μ Steps/s)
4729.79
4741.19
4752.57
4763.92
4775.24
4786.53
4797.80
4800.00
INTERNAL CLOCK CALIBRATION
Timing related functions on the 33991 (e.g., pointer
velocities, acceleration and Return To Zero Pointer speeds)
depend upon a precise, consistent time reference to control
the pointer accurately and reliably. Generating accurate time
references on an Integrated Circuit can be accomplished;
however, they tend to be costly due to the large amount of die
area required for trim pads and the associated trim
procedure. One possibility to reduce cost is an externally
generated clock signal. Another inexpensive approach would
require the use of an additional crystal or resonator.
The internal clock in the 33991 is temperature
independent and area efficient; however, it can vary by as
much as +70 to - 35 percent due to process variation. Using
the existing SPI inputs and the precision timing reference
already available to the controller, the 33991 allows clock
calibration to within ±10 percent.
Calibrating the internal 1MHz clock will be initiated by
writing a logic [1] to PECR bit D3. See Figure 7. The 8 μ s
calibration pulse is provided by the controller. It ideally results
D15
in an internal 33991 clock speed of 1MHz. The pulse is sent
on the CS pin immediately after the SPI word is launched. No
other SPI lines must be toggled. At the moment the CS pin
transitions from logic [1] to [0], an internal 7-bit counter counts
the number of cycles of an internal, non-calibrated, and
temperature independent, 8 MHz clock. The counter stops
when the CS pin transitions from logic [0] to logic [1]. The
value in the counter represents the number of cycles of the 8
MHz clock occurring in the 8 μ s window; it should range from
32 to 119. An offset is added to this number to help center,
or skew the calibrated result to generate a desired maximum
or nominal frequency. The modified counter value is
truncated by four bits to generate the calibration divisor,
ranging from four to 15. The 8 MHz clock is divided by the
calibration divisor, resulting in a calibrated 1 MHz clock. If the
calibration divisor lies outside the range of four to 15, the
33991 flags the ST7 bit, indicating the calibration procedure
was not successful. A clock calibration is allowed only if the
gauges are disabled or the pointers are not moving, indicated
by status bits ST4 and ST5.
D0
CS
SI
SCLK
CSB
PECR Command
8us Calibration Pulse
Figure 8. Gauge Enable and Clock Calibration Example
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires nominal internal clock frequency falls
below 1 MHz. The frequency range of the calibrated clock is
always below 1MHz if PECR bit D4 is logic [0] when initiating
a calibration command, followed by an 8 μ s reference pulse.
The frequency will be centered at 1 MHz if bit D4 is logic [1].
The 33991 can be deceived into calibrating faster or
pulse longer or shorter than the intended 8 μ s. As long as the
count remains between four and 15, there will be no clock
calibration flag. For applications requiring a slower calibrated
clock, i.e., a motor designed with a gear ratio of 120:1 (8
microsteps/degrees), a longer calibration pulse is required.
The device allows a SPI selectable slowing of the internal
oscillator, using the PECR command, so the calibration
divisor safely falls within the four to 15 range when calibrating
slower than the optimal frequency by sending a calibration
33991
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
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