参数资料
型号: MD2202-D96-V3-X
厂商: SANDISK CORP
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PDIP32
封装: DIP-32
文件页数: 13/29页
文件大小: 323K
代理商: MD2202-D96-V3-X
DiskOnChip 2000 DIP
DiskOnChip 2000
Address
Data
Output Enable
Write Enable
Chip Enable
VSS
3.3V or 5V
VCC
D[7:0]
OE#
WE#
CE#
A[12:0]
10 nF
0.1 uF
Figure 7: DiskOnChip 2000 System Interface
Notes: 1. The 0.1 F and the 10 nF low-inductance high-frequency capacitors must be attached to
each of the device’s VCC and VSS pins.
2.
DiskOnChip 2000 is an edge-sensitive device. CE#, OE# and WE# should be
properly terminated (according to board layout, serial parallel, or both terminations)
to avoid signal ringing.
7.3
Connecting Signals
DiskOnChip 2000 uses standard SRAM-like control signals, which should be connected as follows:
Address (A[12:0]) – Connect these signals to the host address bus.
Data (D[7:0]) – Connect these signals to the host data bus.
Write (WE#) and Output Enable (OE#) – Connect these signals to the host WR# and RD#
signals, respectively.
Chip Enable (CE#) – Connect this signal to the memory address decoder.
7.4
Platform-Specific Issues
The following section describes hardware design issues.
7.4.1
Wait State
Wait states can be implemented only when DiskOnChip 2000 is designed in a bus that supports a
Wait state insertion, and supplies a WAIT signal.
7.4.2
Big and Little Endian Systems
PowerPC, ARM, and other RISC processors can use either Big or Little Endian systems.
DiskOnChip 2000 uses the Little Endian system. Therefore, byte D[7:0] is its Least Significant Byte
(LSB); bit D0 is the least significant bit within that byte. When connecting DiskOnChip 2000 to a
20
Data Sheet, Rev. 3.9
91-SR-002-42-8L
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