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ATmega64A [DATASHEET]
8160D–AVR–02/2013
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in
“Clock10.4
Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously (that is, the AS0 bit in ASSR is set), Timer/Counter0 will run during
sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the
corresponding Timer/Counter0 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG
is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-
save mode because the contents of the registers in the asynchronous timer should be considered undefined after
wake-up in Power-save mode if AS0 is 0.
This sleep mode basically halts all clocks except clk
ASY, allowing operation only of asynchronous modules, includ-
ing Timer/Counter0 if clocked asynchronously.
10.5
Standby Mode
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is
kept running. From Standby mode, the device wakes up in six clock cycles.