
52
ATmega64A [DATASHEET]
8160D–AVR–02/2013
sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is
turned off before entering Power-down mode.
11.2
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz. This is the typical value at
V
CC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer pres-
Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a
Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega64A resets and executes from the Reset Vector. For
To prevent unintentional disabling of the Watchdog or unintentional change of Time-out period, three different
safety levels are selected by the fuses M103C and WDTON as shown in
Table 11-1. Safety level 0 corresponds to
the setting in ATmega103. There is no restriction on enabling the WDT in any of the safety levels. Refer to
“TimedFigure 11-7. Watchdog Timer
11.3
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are
described for each level.
Table 11-1.
WDT Configuration as a Function of the Fuse Settings of M103C and WDTON
M103C
WDTON
Safety
Level
WDT Initial
State
How to Disable
the WDT
How to Change
Time-out
Unprogrammed
1
Disabled
Timed
sequence
Timed sequence
Unprogrammed
Programmed
2
Enabled
Always enabled
Timed sequence
Programmed
Unprogrammed
0
Disabled
Timed
sequence
No restriction
Programmed
2
Enabled
Always enabled
Timed sequence
WATCHDOG
OSCILLATOR