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参数资料
| 型号： | MF816M-GNCAVXX |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 5V PROM CARD, 150 ns, XMA68 |
| 文件页数： | 16/22页 |
| 文件大小： | 148K |
| 代理商： | MF816M-GNCAVXX |
MITSUBISHI MEMORY CARD
FLASH MEMORY CARDS
MITSUBISHI
ELECTRIC
3/22
Feb.1999 Rev2.0
FUNCTIONAL DESCRIPTION
The operating mode of the card is determined by
five active low control signals (REG#, CE1#,
CE2#, OE#, WE#), and control registers located in
each memory IC.
Common memory function
When the REG# signal is set to a high level
common memory is selected.
-Read mode
When each memory IC in the card are switched,
the control registers of each memory IC are set to
read only mode.
Operation of the card then depends on the four
possible combinations of CE1# and CE2# (note WE#
should be set to a high level when the device is in read
mode except during combination (4) where it ’ s
condition is unimportant) :
(1) If CE1# is set to a low level and CE2# is set to a
high level, the card will work as an eight bit data
bus width card. Data can be accessed via the
lower half of the data bus (D0 to D7).
(2) If both CE1# and CE2# are set to a low level, data
will be accessible via the full sixteen bit data bus
width of the card. In this mode LSB of address bus
(A0) is ignored.
(3) If CE1# is set to a high level and CE2# is set
to a low level the odd bytes (only) can be
accessed through upper half of the data bus (D8
to D15). This mode is useful when handling the
odd (upper) bytes in a sixteen bit interface
system. Note that A0 is also ignored in this
operating condition.
(4) If CE1# and CE2# are set to a high level, the
card will be in standby mode where it consumes
low power. The data bus is kept high impedance.
When OE# is set to a low level data can be read from
the card, depending on the address applied and the
setting of CE1# and CE2# as mentioned above, except
under combination (4) When OE# is set to a high level
and WE# is set to a high level the card is in an output
disable mode
-Write mode
By using the 4 combinations of CE1# and CE2# as
described under Read only above the appropriate
Data Out and Command/Data In bus selection can be
made.
If OE# is set to a high level and WE# set to a low level,
the control register will latch command data applied
at the rising edge of the WE# signal. Note that more
than one bus cycle may be required to latch the
command and/or the related data-please refer to the
Command Definition table.
If OE# is set to a low level and WE# is set to a high
level the card data can be read from the card
depending on the condition of the control register.
After latching the command data, the card will go into
programming, erasure or other operation mode. For
details please refer to the Command Definition table,
each individual command ’ s definition and the
programming and erasure algorithms.
Attribute memory function
When the REG# signal is set to a low level attribute
memory is selected.
GM series
The card includes a byte wide attribute memory
consisting of 8K bytes of E
2 PROM located at the even
addresses when the card is in the 8 bit
operating mode. It is located at sequential
addresses on the lower half of the data bus when
the card is in 16 bit operating mode i.e. A0 is
ignored.
To access the attribute memory, first set CE1# and
CE2#. Set CE1# to low level and CE2# to high level
for 8 bit mode or CE1# and CE2# to low level for 16
bit mode. Then select the required address. Note
please take care that in 8 bit mode A0 must be set low
for attribute memory access i.e. an even address is
applied. In 16 bit mode it is not important whether A0
is high or
low. Data can then be read by setting OE# to a low
level with WE set to a high level.
Writing to the attribute memory can be achieved
in byte mode only. To write to attribute memory set
OE# to high level and WE# to low level. The data to
be written will be latched at the rising edge of WE#.
Then, unless WE# changes back
from high level to low level over 100 s an
automatic erase/program operation starts which will
complete within 10ms.
Please also remember that for attribute memory A0 is
not applicable and it should be set to low, even
addressing only, in 8 bit mode or ignored for 16 bit
mode.
GN series
The card then outputs FFh on the lower half of the
data bus (D0 to D7) when the following conditions
are applied;
(1)CE1#=low level,CE2#=high level,OE#=low
level,WE#=high level,A0=low level.
(2)CE1#=low level,CE2#=low level,OE#=low
level,WE#=high level.
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