参数资料
| 型号： | MIC2199BML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 12-MLF |
| 标准包装： | 5,000 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 32 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 12-VFDFN 裸露焊盘，12-MLF? |
| 包装： | 带卷 (TR) |
| 其它名称： | MIC2199BMLTR MIC2199BMLTR-ND |
Micrel, Inc.
Voltage Setting Components
The MIC2199 requires two resistors to set the output voltage
as shown in Figure 6.
MIC2199
To maximize efficiency at light loads:
? Use a low gate-charge MOSFET or use the small -
est MOSFET, which is still adequate for maximum
output current.
MIC2199
Error
Amp
V REF
0.8V
FB
3
R1
R2
? Use a ferrite material for the inductor core, which
has less core loss than an MPP or iron power
core.
Under heavy output loads the significant contributors to power
loss are (in approximate order of magnitude):
? Resistive on-time losses in the MOSFETs
? Switching transition losses in the MOSFETs
V O = V REF × ? 1 + ?
V REF × R1
I DIVIDER = REF
P DIVIDER = (R1 + R2) × I DIVIDER
Figure 6. Voltage-Divider Configuration
The output voltage is determined by the equation:
? R1 ?
? R2 ?
Where: V REF for the MIC2199 is typically 0.8V.
A typical value of R1 can be between 3k and 10k. If R1 is
too large it may allow noise to be introduced into the volt-
age feedback loop. If R1 is too small in value it will decrease
the efficiency of the power supply, especially at low output
loads.
Once R1 is selected, R2 can be calculated using:
R2 =
V O ? V REF
Voltage Divider Power Dissipation
The reference voltage and R2 set the current through the
voltage divider.
V
R2
The power dissipated by the divider resistors is:
2
Efficiency Calculation and Considerations
Efficiency is the ratio of output power to input power. The
difference is dissipated as heat in the buck converter. Under
light output load, the significant contributors are:
? Supply current to the MIC2199
? MOSFET gate-charge power (included in the IC
supply current)
? Core losses in the output inductor
? Inductor resistive losses
? Current-sense resistor losses
? Input capacitor resistive losses (due to the capaci -
tors ESR)
To minimize power loss under heavy loads:
? Use logic-level, low on-resistance MOSFETs.
Multiplying the gate charge by the on-resistance
gives a figure of merit, providing a good balance
between low and high load efficiency.
? Slow transition times and oscillations on the voltage
and current waveforms dissipate more power during
turn-on and turnoff of the MOSFETs. A clean layout
will minimize parasitic inductance and capacitance
in the gate drive and high current paths. This will
allow the fastest transition times and waveforms
without oscillations. Low gate-charge MOSFETs
will transition faster than those with higher gate-
charge requirements.
? For the same size inductor, a lower value will
have fewer turns and therefore, lower winding re-
sistance. However, using too small of a value will
require more output capacitors to filter the output
ripple, which will force a smaller bandwidth, slower
transient response and possible instability under
certain conditions.
? Lowering the current-sense resistor value will
decrease the power dissipated in the resistor.
However, it will also increase the overcurrent
limit and will require larger MOSFETs and inductor
components.
? Use low-ESR input capacitors to minimize the
power dissipated in the capacitors ESR.
January 2010
12
M9999-011310
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