参数资料
型号: MIC2341-2YTQ TR
厂商: Micrel Inc
文件页数: 25/32页
文件大小: 1277K
描述: IC HOT PLUG CTLR DUAL PCI 48TQFP
标准包装: 2,000
类型: 热交换控制器
应用: 通用型,PCI Express?
内部开关:
电流限制: 可调
电源电压: 3.3V,12V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-TQFP
供应商设备封装: 48-TQFP(7x7)
包装: 带卷 (TR)
Micrel, Inc.
MIC2341/2341R
 
 
October 2007 
25
M9999-102507-A
 (408) 944-0800
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
X
0
1     UV     X
X
X
X
X
X
X
X
X
0
1
X
0
1
X     UV     X
X
X
X
X
X
X
X
0
X
1
0
1
X
X     UV     X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
0
1     UV     X
X
0
X
X
X
X
X
X
X
1
X
0
1
X     UV     X
0
X
X
X
X
X
X
X
X
1
0
1
X
X     UV     0
 
where 1 = Logic HIGH
0 = Logic LOW
X = Dont care
 
Table 1. SYSPWRGD Truth Table
 
 
 
 
 
 
Hardware Interface
Once the input power supply voltages are above their
respective UVLO thresholds, the MIC2341/MIC2341Rs
hardware interface can be enabled for power control by
asserting    the    control    input    pins    (/CRSW[A/B],
AUXEN[A/B], and ON[A/B]) appropriately for each slot.
The MIC2341/MIC2341Rs ON[A/B] and AUXEN[A/B]
signals are asserted active-HIGH, level-sensitive digital
inputs with internal pull-up
 45k& resistors to VSTBY[A]
to save pc board area and external component costs. As
such, external hot-plug controllers connecting to these
pins should configure their respective output drivers to
OPEN-DRAIN and configure their firmware to de-assert
these signals to turn OFF either the MAIN[A/B] outputs
or the VAUX[A/B] outputs. As these input control signals
are already asserted after POR, the corresponding
/CRSW[A/B] control signal should be used to enable the
slots gate drive circuits to initiate a power-up sequence.
For example, in order for the MIC2341/MIC2341R to
switch   on   the   VAUX   supply   for   either   slot,   the
AUXEN[A/B] control can be enabled during or after the
power-on-reset operation (typically, t
POR
  = 160祍. The
timing response diagram of Figure 9 illustrates the
hardware interface operation where an overcurrent fault
is detected by the MIC2341/MIC2341R controller after
initiating a power-up sequence. The MAIN (+12V &
+3.3V) and VAUX[A/B] supply rails, /FAULT, /PWRGD
and /INT output responses for both AUX and MAIN are
shown in the figure.
 
 
 
 
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