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参数资料
| 型号： | MIC2591B-5YTQ |
| 厂商： | MICREL INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 15/34页 |
| 文件大小： | 1920K |
| 代理商： | MIC2591B-5YTQ |
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MIC2591B
Micrel
March 2005
22
M9999-033105
target address, with the R/W bit (LSB) set to the low (write)
state,followedbyacommandbyteandadatabyte.TheSMBus
Read_Byte operation is similar, but is a composite write and
readoperation:thehostrstsendsthedevice’stargetaddress
followed by the command byte, as in a write operation. A new
“Start” bit must then be sent to the MIC2591B, followed by a
repeat of the device address with the R/W bit set to the high
(read) state. The data to be read from the part may then be
clocked out. There is one exception to this rule: If the location
latched in the pointer register from the last write operation is
known to be correct (i.e., points to the desired register within
the MIC2591B), then the “Receive_Byte” procedure may be
used. To perform a Receive_Byte operation, the host sends
an address byte to select the target MIC2591B, with the R/W
bit set to the high (read) state, and then retrieves the data
byte. Figures 10 through 12 show the formats for these data
read and data write procedures.
The Command Register is eight bits (one byte) wide. This
byte carries the address of the MIC2591B’s register to be
operated upon. The command byte values corresponding to
the various MIC2591B register addresses are shown in Table
2. Command byte values other than 0000 0XXXb = 00h - 07h
are reserved and should not be used.
MIC2591B SMBus Address Conguration
The MIC2591B responds to its own unique SMBus address,
which is assigned using A2, A1, and A0. These represent
the 3 LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
VSTBY[A/B] supply input. These address bits allow up to
eight MIC2591B devices in a single system. These pins are
either grounded or left unconnected to specify a logical 0 or
logical 1, respectively. A pin designated as a logical 1 may
also be pulled up to VSTBY.
STBY
S 1 0 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 X X A
D4
D5
D6
D3 D2 D1 D0
D7
A P
MIC2591B Device Address
DATA
CLK
Command Byte to MIC2591B
Data Byte to MIC2591B
START
STOP
R/W = WRITE
ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 10. WRITE_BYTE Protocol
S 1 0 0 0 A2 A1 A0
A2 A1 A0
0 A 0 0 0 0 0 0 X X A S 1
0
1
0 0
D4
D5
D6
D3 D2 D1 D0
A D7
/A P
MIC2591B Device Address
DATA
CLK
Command Byte to MIC2591B
MIC2591B Device Address
Data Read From MIC2591B
START
STOP
R/W = WRITE
R/W = READ
ACKNOWLEDGE
ACKNOWLEDGE NOT ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 11. READ_BYTE Protocol
S 1 0 0 0 A2 A1 A0 1 A
D4
D5
D6
D3 D2 D1 D0
D7
/A P
MIC2591B Device Address
DATA
CLK
Byte Read from MIC2591B
START
STOP
R/W = READ
ACKNOWLEDGE NOT ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 12. RECEIVE_BYTE Protocol
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