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参数资料
| 型号： | MIC4744YTSE |
| 厂商： | Micrel Inc |
| 文件页数： | 9/23页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A DL 16TSSOP |
| 标准包装： | 94 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 可调至 0.6V |
| 输入电压： | 2.9 V ~ 5.5 V |
| 频率 - 开关： | 4MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 16-EPAD TSSOP |
| 产品目录页面： | 1093 (CN2011-ZH PDF) |
| 其它名称： | 576-3357-5 |
Micrel, Inc.
Pin Description
VIN1/VIN2
VIN pins (two pins for VIN1 and two pins for VIN2)
provide power to the source of the internal P-Channel
MOSFET along with the current limiting sensing. VIN1
pins and VIN2 pins are internally connected by anti-
parallel diodes. The VIN operating voltage range is from
2.9V to 5.5V. Due to the high switching speeds, a 10μF
capacitor is recommended close to VIN and the power
ground (PGND) for each pin for bypassing. Please refer
to layout recommendations for more details.
BIAS
The bias (BIAS) provides power to the internal reference
and control sections of the MIC4744. A 10 ? resistor
from VIN to BIAS and a 0.1μF from BIAS to SGND are
required for clean operation.
EN1/EN2
The enable pins (EN1 and EN2) provides a logic level
control of the outputs 1 and 2. In the off state, supply
current of the device is greatly reduced (typically <2μA).
Do not drive the enable pin above the supply voltage.
FB1/FB2
The feedback pins (FB1 and FB2) provides the control
path to control the outputs 1 and 2. A resistor divider
connecting the feedback to the output is used to adjust
the desired output voltage. The output voltage is
calculated as follows:
MIC4744
SW1/SW2
The switch pins (SW1 and SW2) connect directly to the
inductor and provide the switching current necessary to
operate in PWM mode. Due to the high speed switching
on these pins, the switch nodes should be routed away
from sensitive nodes. These pins also connect to the
cathodes of the free-wheeling diodes.
PGND1/PGND2
Power ground pins (PGND1 and PGND2) are the ground
paths for the MOSFET drive current. PGND1 pin and
PGND2 pin are internally connected by anti-parallel
diodes. The current loop for the power ground should be
as small as possible and separate from the Signal
ground (SGND) loop. Refer to the layout
recommendation for more details.
SGND
Signal ground (SGND) is the ground path for the biasing
and control circuitry. The current loop for the signal
ground should be separate from the power ground
(PGND) loop. Refer to the layout recommendation for
more details.
EPAD
The exposed pad on the bottom of the part must be
connected to ground.
V OUT = V REF × ?
+ 1 ?
? R1
? R2
?
?
where V REF is equal to 0.6V.
A feed-forward capacitor is recommended for most
designs. To reduce current draw, 10K feedback resistors
are recommended from the outputs to the FB pins (R1 in
the equation). Also, feed-forward capacitors should be
connected between the outputs and feedback pins
(across R1). The large resistor value and the parasitic
capacitance of the FB pin can cause a high frequency
pole that can reduce the overall system phase margin.
By placing a feed-forward capacitor, these effects can be
significantly reduced. Feed-forward capacitance (C FF )
can be calculated as follows:
C FF =
1
2 π × R1 × 200kHz
March 2009
9
M9999-030209-C
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