参数资料
型号: MK1574-01ASLFTR
元件分类: 时钟及定时
英文描述: 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, SOIC-16
文件页数: 4/10页
文件大小: 146K
代理商: MK1574-01ASLFTR
FRAME RATE COMMUNICATIONS PLL
MDS 1574-01A/B B
3
Revision 051206
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01A/B
Pin Descriptions
External Components
The MK1574-01A/B requires a minimum number of external components for proper operation. An RC
network (see the section “Loop Bandwidth and Loop Filter Component Selection”) should be connected
between CAP1 and CAP2 as close tot he device as possible. Decoupling capacitors of 0.01F should be
connected between VDD and GND on pins 2, 3, 5 and 7, as close to the device as possible. A series
termination resistor of 33
may be used close to each clock output pin to reduce reflections.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock input. Connect to an 8 kHz clock input.
2
VDD
Power Connect to 3.3 V for 1574-01B, Connect to 5 V for 1574-01A.
3
VDD
Power Connect to 3.3 V for 1574-01B, Connect to 5 V for 1574-01A.
4
CAP1
Input
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
5
GND
Power Connect to ground.
6
CAP2
Power Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
7
GND
Power Connect to ground.
8
FS0
Input
Frequency select 0. Determines CLK outputs per table above.
9
8KOUT
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
input.
10
CLK1
Output Clock 1 determined by status of FS3:0 per table above.
11
CLK2
Output Clock 2 determined by status of FS3:0 per table above.
12
CLK3
Output Clock 3 determined by status of FS3:0 per table above.
13
FS1
Input
Frequency select 1. Determines CLK outputs per table above.
14
FS2
Input
Frequency select 2. Determines CLK outputs per table above.
15
NC
No connect. Do not connect anything to this pin.
16
FS3
Input
Frequency select 3. Determines CLK outputs per table above.
相关PDF资料
PDF描述
MK1574-01BSTRLF 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASTR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASITR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01SLFTR PLL BASED CLOCK DRIVER, PDSO16
MK1574-01S PLL BASED CLOCK DRIVER, PDSO16
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