参数资料
型号: MK1574-01ASLFTR
元件分类: 时钟及定时
英文描述: 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, SOIC-16
文件页数: 8/10页
文件大小: 146K
代理商: MK1574-01ASLFTR
FRAME RATE COMMUNICATIONS PLL
MDS 1574-01A/B B
7
Revision 051206
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01A/B
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the
dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a
high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine
the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore
a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and
X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the
system to increase the output jitter because the mechanical energy is converted directly to voltage noise
on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter
components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7).
The loop bandwidth is set by the capacitor C and the constant K1 using the formula:
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page
7) shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using
equation 1,
Therefore,
3. A good value for the damping factor
ζ is 0.707. From equation 2,
BW (Hz) =
C
K1
Equation 1
R =
Equation 2;
ζ (zeta) is the damping factor
C
ζ * K2
C
K1
400 =
C
K1
C =
400
0.0516
(
) 2
= 16.6 nF (16 nF nearest standard value
R =
= 34.7 k
(36 k nearest standard value)
16E-9
0.707 * 6.2
相关PDF资料
PDF描述
MK1574-01BSTRLF 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASTR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASITR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01SLFTR PLL BASED CLOCK DRIVER, PDSO16
MK1574-01S PLL BASED CLOCK DRIVER, PDSO16
相关代理商/技术参数
参数描述
MK1574-01ASTR 功能描述:时钟发生器及支持产品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MK1574-01BS 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器,扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP(8x8) 包装:带卷 (TR) 其它名称:844S012AKI-01LFT
MK1574-01BSI 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:*
MK1574-01BSILF 功能描述:时钟发生器及支持产品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MK1574-01BSILFTR 功能描述:时钟合成器/抖动清除器 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel