参数资料
型号: MK1574-01ASLFTR
元件分类: 时钟及定时
英文描述: 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, SOIC-16
文件页数: 9/10页
文件大小: 146K
代理商: MK1574-01ASLFTR
FRAME RATE COMMUNICATIONS PLL
MDS 1574-01A/B B
8
Revision 051206
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01A/B
Loop Filter Constants
This table shows the constants K1 and K2 that are used with the equations on page 6 to calculate the external loop
filter components.Loop Filter Contstants for MK1574-01A
PC Board Layout
A proper board layout is critical to the successful use of the MK1574-01A/B. In particular, the CAP1 and
CAP2 pins are very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be
as short as possible and the capacitor and resistor must be mounted next to the device as shown to the
right. The capacitor connected between pins 3 and 5 is the power supply decoupling capacitor. The high
frequency output clocks on may benefit from a series 33
resistor connected close to the pin (not shown).
Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574-01A/B ROM, which yield the exact
values shown for the output clocks.
Decode
Address
Loop Filter Constants
FS3:0
(Hex)
K1
K2
0000
0
Reserved
0001
1
Reserved
0010
2
Reserved
0011
3
Reserved
0100
4
0.0430
7.4
0101
5
0.0527
6.0
0110
6
0.0444
7.2
0111
7
0.0454
7.0
1000
8
0.0533
6.0
1001
9
0.0410
7.8
1010
A
0.0508
6.3
1011
B
0.0587
5.4
1100
C
0.0365
8.7
1101
D
0.0420
7.6
1110
E
0.0516
6.2
1111
F
0.0594
5.4
相关PDF资料
PDF描述
MK1574-01BSTRLF 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASTR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASITR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01SLFTR PLL BASED CLOCK DRIVER, PDSO16
MK1574-01S PLL BASED CLOCK DRIVER, PDSO16
相关代理商/技术参数
参数描述
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