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参数资料
| 型号： | MK1575-01GLFTR |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-16 |
| 文件页数： | 5/12页 |
| 文件大小： | 217K |
| 代理商： | MK1575-01GLFTR |
CLOCK RECOVERY PLL
MDS 1575-01 L
2
Revision 070605
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK1575-01
Pin Assignment
16 pin 4.40 mil body, 0.65 mil pitch TSSOP
Pin Descriptions
12
1
11
2
10
REFIN
FBIN
3
9
FS0
4
VDDA
NC
5
VDDD
6
FCLK
7
FS1
8
GNDA
OE
CLK2
FS2
GNDD
CLK1
CHGP
CHPR
16
15
14
13
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
REFIN
Input
Reference clock input. Connect the input clock to this pin. Can be
Rising or Falling edge triggered as per Detailed Mode Selection Table,
page 3.
2FS0
Input
Frequency Selection Input bit 0, selects internal divider values as per
Detailed Mode Selection Table, page 3.
3
VDDA
Power
Power supply connection for internal VCO and other analog circuits.
4
VDDD
Power
Power supply connection for internal digital circuits and output buffers.
5FS1
Input
Frequency Selection Input bit 1, selects internal divider values as per
Detailed Mode Selection Table, page 3.
6
GNDA
Ground
Ground connection for internal VCO and other analog circuits.
7
GNDD
Ground
Ground connection for internal digital circuits and output buffers.
8
CHGP
—
Loop filter connection, active node.
9
CHPR
—
Loop filter connection, reference node. Do not connect to ground.
10
CLK1
Output
Output clock 1.
11
FS2
Input
Frequency Selection Input bit 2, selects internal divider values as per
Detailed Mode Selection Table, page 3.
12
CLK2
Output
Output clock 2.
13
OE
Input
Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL
when high. Internal pull-up.
14
FCLK
Output
Feedback clock output, connect to FBIN for the pre-configured
frequency combinations listed in the tables on page 1.
15
NC
—
No internal connection, connect to ground.
16
FBIN
Input
Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of
an external feedback divider, depending on application. Refer to
document text for more information.
相关PDF资料 |
PDF描述 |
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| MK1575-01GI | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1575-01G | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1575-01GITR | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
| MK1581-01GI | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK1581-01GILF | 功能描述:时钟发生器及支持产品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1581-01GILFTR | 功能描述:时钟发生器及支持产品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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