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参数资料
| 型号： | MK2048-01SLFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 1/5页 |
| 文件大小： | 74K |
| 代理商： | MK2048-01SLFTR |
MK2048
Communications Frequency Generator
MDS 2048-01 B
1
Revision 022598
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
I C R O
C LOC K
Packaged in 16 pin narrow (150 mil) SOIC
Accepts multiple inputs: 8kHz backplane clock,
12.288 MHz crystal, and Loop Timing frequencies
Exact ratios stored in the device eliminate the need
for external dividers
Patented design give zero ppm synthesis error in all
output clocks.
Output clock rates include T1, E1, T3, E3, OC3
5V ±10% operation
The MK2048 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
12.288 MHz crystal input. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an 8
kHz backplane clock, simplifying clock
distribution in communications systems.
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
Block Diagram
Description
Features
Crystal
Oscillator
VDD GND
PLL
Clock
Synthesis
and Control
Circuitry
X1
X2
12.288 MHz
crystal
Output
Buffer
CLK1
Output
Buffer
CLK2
External/
Loop Timing
Mux
ROM
Divider
Crystal/
Clock
Select
FS3:0
Clock
Input
2
CAP1
CAP2
2
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相关代理商/技术参数 |
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|---|---|
| MK2049-01 | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01S | 制造商:Integrated Device Technology Inc 功能描述:IC SM CLK GEN T1/E1/T3/E3 PLL 8KHZ P-SO- - Bulk |
| MK2049-01SI | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01SITR | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01STR | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 20SOIC - Tape and Reel |
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