- 您现在的位置：买卖IC网 > PDF目录80516 > MK2048-01SLFTR 77.76 MHz, OTHER CLOCK GENERATOR, PDSO16 PDF资料下载
参数资料
| 型号： | MK2048-01SLFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 4/5页 |
| 文件大小： | 74K |
| 代理商： | MK2048-01SLFTR |
MK2048
Communications Frequency Generator
MDS 2048-01 B
4
Revision 022598
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
I C R O
C LOC K
The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The values
of the RC network determine the bandwidth of the PLL.
The attenuation of the jitter on the ICLK input improves with decreasing values of R and increasing values of
C, until a point is reached where the startup time becomes unacceptably long. A good starting point is
0.1 F and 1 k
. The optimum values should be determined by the spectral characteristics of the ICLK
jitter.
The following formula gives the approximate loop bandwidth for the MK2048:
where:
fbw is the loop bandwidth in Hertz
fclk1 is the frequency of CLK1 in Hertz
C is the value of capacitor in Farads
For example, if CLK1 is running at 24MHz and C=0.1 F, then
fbw =
fclk1 C
537
fbw =
537
24x106 1x10-7
= 347 Hz
Loop Bandwidth and Loop Filter Component Selection
If minimum absolute jitter is required, the RC network should be replaced by a single capacitor with a value
between 0.01F and 2F. Larger values will cause the PLL to start more slowly. For example, if C=2F, the
loop may take several seconds to start.
Do not print this page. The equation needs to be
modified for the MK2048 dividers. Jan is to do
this when he gets time.
5/23/97
PC Board Layout
A proper board layout is critical to the successful
use of the MK2048. In particular, the CAP1 and
CAP2 pins are very sensitive to noise and leakage
(CAP1 at pin 4 is the most sensitive). Traces
must be as short as possible and the capacitor
and resistor must be mounted next to the device
as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply
decoupling capacitor.
The high frequency output clocks on pins 10 and
11 may benefit from a series 33
resistor
connected close to the pin (not shown).
1
2
3
4
5
6
7
8
G
V
=connect to VDD
=connect to GND
V
G
16
15
14
13
12
11
10
9
cap
resist.
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC11K4MFN2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC711K4MFN4 | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQCC84 |
| MC68L11K4FU3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP80 |
| MPC8347EVRAGDA | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620 |
| MPC8349EVVALFA | 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-01 | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01S | 制造商:Integrated Device Technology Inc 功能描述:IC SM CLK GEN T1/E1/T3/E3 PLL 8KHZ P-SO- - Bulk |
| MK2049-01SI | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01SITR | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLL |
| MK2049-01STR | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 20SOIC - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。