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参数资料
| 型号： | MK2049-44SILF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 6/9页 |
| 文件大小： | 176K |
| 代理商： | MK2049-44SILF |
3.3V Communications Clock PLL
MDS 2049-44 A
6
Revision 050203
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK2049-44
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on Page 7.
1) Each 0.01 F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The loop filter components must also be placed
close to the CHGP and VIN pins. CP should be closest
to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces
short and away from active signal traces. Use of vias
should be avoided.
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
4) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2049-44.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
MAN05 may also be referenced for additional
suggestions on layout of the crystal section.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-44. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
-40 to +85
°C
Storage Temperature
-65 to +150
°C
Junction Temperature
175
°C
Soldering Temperature
250
°C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-45 | 制造商:ICS 制造商全称:ICS 功能描述:3.3V Communications Clock PLL |
| MK2049-45ASI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45ASILF | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASILFTR | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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