- 您现在的位置：买卖IC网 > PDF目录132980 > MK2069-02GI 160 MHz, OTHER CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | MK2069-02GI |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 20/20页 |
| 文件大小： | 347K |
| 代理商： | MK2069-02GI |
VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
9
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
Example Loop Filter Component Values
Notes:
1) The above examples illustrate the ability to adjust the VCXO PLL loop bandwidth by changing the PV
Divider setting only. Settings of the Translator PLL do not affect the VCXO PLL loop bandwidth, so a TCLK
output frequency of 77.76 MHz or 155.52 MHz could be present, for example, with any of the above
configurations. A VCXO gain (Kvco) of 4200 MHz/V was used for all bandwidth calculations.
2) The top group of settings use a minimal sized loop filter capacitor CS which minimizes cost and board
space.
3) The middle group of settings use a larger sized loop filter capacitor CP allowing a lower PV Divider setting
for similar bandwidth and damping performance. This provides a higher phase detector frequency (equal to
the RCLK frequency, as shown) which is needed in applications subject to higher frequency reference clock
jitter to avoid jitter aliasing. Note that a higher phase detector frequency reduces jitter tolerance as well.
4) The bottom group of settings also use a larger sized loop filter capacitor CS, but an increased PV Divider
setting to achieve higher damping factors. A damping factor of 4 or higher is required to assure a passband
ripple of <0.2 dB which is required to comply with the Bellcore GR-1244-CORE wander transfer limit. The
value of CP also must not be excessive.
5) This setting would be a good choice for many 19.44 MHz jitter attenuation applications. It could be used,
for example, when following a system synchronizer such as the MT9045 to provide clock jitter attenuation
while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output generated with this VCXO PLL
configuration will be OC-3 and OC-12 timing jitter compliant. The 80 Hz bandwidth is high enough to allow the
MT9045 jitter transfer characteristics to dominate, yet low enough to provide good jitter attenuation. The
passband peak occurs past the MT9045 frequency roll-off point, further protecting against excessive wander
transfer gain. This higher loop bandwidth also provides improved stability of the VCXO circuit.
Input
(ICLK)
Frequency
Xtal
Freq
(MHz)
VCLK
(MHz)
RCLK
(MHz)
PV
Div
FV
Div
SV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Notes
19.44 MHz
19.44
0.008 2430
11
1 M
560 k 0.1 F1 nF
24 Hz
1.3
1 dB at 5Hz
2
19.44 MHz
19.44
19.44 0.0162 1200
11
1 M
560 k 0.1 F1 nF
48 Hz
1.9
0.5 dB at 7Hz
2
19.44 MHz
19.44
19.44 0.0324 600
11
1 M
560 k 0.1 F1 nF 110 Hz
2.6
0.3 dB at 10Hz
2
19.44 MHz
19.44
19.44 0.6075
32
11
2 M
22 k
1
F
22 nF
38 Hz
1
1.5 dB at 11Hz
3
19.44 MHz
19.44
1.215
16
11
2 M
22 k
1
F
22 nF
70 Hz
1.4
0.75dB at 13Hz
3
19.44 MHz
19.44
9.72
2
11
2 M
22 k
1
F
22 nF 550 Hz
4
0.15dB at 30Hz
3
19.44 MHz
19.44
19.44 0.0648 300
11
2 M
168 k 1 F
4.7 nF
30 Hz
2.5
0.3dB at 3Hz
4
19.44 MHz
19.44
0.162
120
11
2 M
168 k 1 F
4.7 nF
80 Hz
4
0.15dB at 5Hz
4,5
19.44 MHz
19.44
0.249
78
11
2 M
168 k 1 F
4.7 nF 140 Hz
5
0.15dB at 10Hz
4
相关PDF资料 |
PDF描述 |
|---|---|
| MC68882CFN16A | 32-BIT, MATH COPROCESSOR, PQCC68 |
| MC68882CFN20A | 32-BIT, MATH COPROCESSOR, PQCC68 |
| MC68882CFN33A | 32-BIT, MATH COPROCESSOR, PQCC68 |
| MC68882CRC20A | 32-BIT, MATH COPROCESSOR, CPGA68 |
| MC68882CRC33A | 32-BIT, MATH COPROCESSOR, CPGA68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2069-03 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| MK2069-03GITR | 功能描述:时钟发生器及支持产品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。