VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
12
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2069-02 and the
crystal.
Recommended Crystal Parameters:
Crystal parameters can be found in application note
Crystal Tuning Load Capacitors
The crystal traces should include pads for small
capacitors from X1 and X2 to ground, shown as CL in
the External VCXO PLL Components diagram on page
6. These capacitors are used to center the total load
capacitor adjustment range imposed on the crystal.
The load adjustment range includes stray PCB
capacitance that varies with board layout. Because the
typical telecom reference frequency is accurate to less
than 32 ppm, the MK2069-02 may operate properly
without these adjustment capacitors. However, ICS
recommends that these capacitors be included to
minimize the effects of variation in individual crystals,
including those induced by temperature and aging. The
value of these capacitors (typically 0-4 pF) is
determined once for a given board layout, using the
procedure described in
MAN05.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please refer to the Recommended PCB
Layout drawing on the following page.
1) Each 0.01F decoupling capacitor (CD) should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between the decoupling capacitor and VDD pin. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite chip and bulk decoupling from
the device is less critical.
2) The loop filter components must also be placed
close to the LF and LFR pins. CP should be closest to
the device. Coupling of noise from other system signal
traces should be minimized by keeping traces short
and away from active signal traces. Use of vias should
be avoided.
3) The external crystal should be mounted as close to
the device as possible, on the component side of the
board. This will help keep the crystal PCB traces short
to minimize parasitic load capacitance on the crystal
leads as well as noise pickup. The crystal traces should
be spaced away from each other and should use
minimum trace width. There should be no signal traces
near the crystal or the traces. Also refer to the Optional
Crystal Shielding section that follows.
4) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
5) All components should be on the same side of the
board, minimizing vias through other signal layers (the
ferrite bead and bulk decoupling capacitor may be
mounted on the back). Other signal traces should be
routed away from the MK2069-02. This includes signal
traces on PCB traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
6) Because each input selection pin includes an
internal pull-up device, those inputs requiring a logic
high state (“1”) can be left unconnected. The pins
requiring a logic low state (“0”) can be grounded.