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参数资料
| 型号： | MK2069-04GI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 2/21页 |
| 文件大小： | 410K |
| 代理商： | MK2069-04GI |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
10
MK2069-04
REV J 051310
conjunction with an external multiplexer (MUX), CLR should
be brought low prior to MUX reselection, then returned high
after MUX reselection. This prevents the VCXO PLL from
attempting to lock to the new input clock phase associated
with the input clock.
When CLR is high, the VCXO PLL operates normally.
When CLR is low, the VCXO PLL charge pump output is
inactivated which means that no charge pump correction
pulses are provided to the loop filter. During this time, the
VCXO frequency is held constant by the residual charge or
voltage on the PLL loop filter, regardless of the input clock
condition. However, the VCXO frequency will drift over time,
eventually to the minimum pull range of the crystal, due to
leak-off of the loop filter charge. This means that CLR can
provide a holdover function, but only for a very short
duration, typically in milliseconds.
Upon bringing CLR high, the FV Divider is reset and begins
counting upon with the first positive edge of the new input
clock, and the charge pump is re-activated. By resetting the
FV Divider, the memory of the previous input clock phase is
removed from the feedback divider, eliminating the
generation of extra VCLK clock cycles that would occur if the
loop was to re-lock under normal means. Lock time is also
reduced, as is the generation of clock wander.
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips resulting.
When CLR is not used, the number of VCLK cycle slips can
be as high the FV Divider value.
TCLK is always locked to VCLK regardless of the state of
the CLR input.
Lock Detection
The MK2069-04 includes a lock detection feature that
indicates lock status of VCLK relative to the selected input
reference clock. When phase lock is achieved (such as
following power-up), the LD output goes high. When phase
lock is lost (such as when the input clock stops, drifts beyond
the pullable range of the crystal, or suddenly shifts in
phase), the LD output goes low.
The definition of a “locked” condition is determined by the
user. LD is high when the VCXO PLL phase detector error
is below the user-defined threshold. This threshold is set by
external components RLD and CLD shown in the Lock
Detection Circuit Diagram, below.
To help guard against false lock indications, the LD pin will
go high only when the phase error is below the set threshold
for 8 consecutive phase detector cycles. The LD pin will go
low when the phase error is above the set threshold for only
1 phase detector cycle.
The lock detector threshold (phase error) is determined by
the following relationship:
(LD Threshold) = 0.6 x R x C
Where:
1 k
< R < 1 M (to avoid excessive noise or leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
Lock Detector Application example:
The desired maximum allowable loop phase error for a
generated 19.44 MHz clock is 100UI which is 5.1
s.
Solution: 5.1
s = (0.001 F) x (8.5 k)
Under ideal conditions, where the VCXO is phase- locked to
a low-jitter reference input, loop phase error is typically
maintained to within a few nanoseconds.
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