- 您现在的位置：买卖IC网 > PDF目录9145 > MK2069-04GILF (IDT, Integrated Device Technology Inc)IC CLOCK SYNTHESIZER 56-TSSOP PDF资料下载
参数资料
| 型号： | MK2069-04GILF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 标准包装： | 34 |
| 类型： | 时钟同步器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1254 (CN2011-ZH PDF) |
| 其它名称： | 800-1783 800-1783-5 800-1783-ND |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
5
MK2069-04
REV J 051310
Application Information
The MK2069-04 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
RPV Divider = 1 or 8
RV Divider = 2 to 4097
Because the RPV divider inherently has a higher speed of
operation than the RV divider, the RPV divider should be set
to 8 when this factor is included in the RPV x RV divisor
combination.
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
the pullable range of the crystal. This is guaranteed to be
±115 ppm minimum. This tracking range in ppm also applies
to the input clock and all clock outputs if the device is to
remain frequency locked to the input, which is required for
normal operation.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 2, 4, 6, 8, 10, 12, 14 or 16
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-04 Loop Response and JItter
Attenuation Characteristics
The MK2069-04 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
through the selection of external MK2069-04 passive
components and other device setting as explained in the
following section.
f(VCLK)
FV Divider
RPV Divider
RV Divider
×
-------------------------------------------------------------------
f(ICLK)
×
=
f(VCLK)
fVCXO
()
SV Divider
-----------------------
=
f(TCLK)
FT Divider
f(VCLK)
×
=
f(TCLK)
f(VCO)
ST Divider
-----------------------
=
相关PDF资料 |
PDF描述 |
|---|---|
| X9420WS16-2.7 | IC DIGITAL POT 10K 64TP 16SOIC |
| X9420WS16 | IC DIGITAL POT 10K 64TP 16SOIC |
| X9418WV24I | IC DCP DUAL 10K 64TP 24TSSOP |
| ICS843001AGI-22LF | IC SYNTHESIZER LVPECL 24-TSSOP |
| X9418WV24-2.7 | IC DCP DUAL 10K 64TP 24TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2069-04GILFTR | 功能描述:时钟发生器及支持产品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK206N 454634/1/MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; For Use With:Rotary Switches; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact ;RoHS Compliant: Yes |
| MK206S 454634MK | 制造商:NSF (CONTROLS) 功能描述:WAFER MK 2POLE 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS 制造商:NSF (CONTROLS) 功能描述:WAFER, MK, 2POLE, 6 POS; No. of Poles:2; No. of Positions:6; SVHC:No SVHC (19-Dec-2012); Contact Current @ Contact Voltage AC Max:500mA; Contact Current AC Max:5A; Contact Current DC Max:5A; Contact Current Rating:5A; Contact ;RoHS Compliant: Yes |
| MK20-B-100W | 功能描述:近程传感器 1 Form A Cylindrical Term. RoHS:否 制造商:Vishay Semiconductors 感应方式:Optical 感应距离:1 mm to 200 mm 电源电压:2.5 V to 3.6 V 安装风格:SMD/SMT 输出配置:Digital 最大工作温度:+ 85 C 最小工作温度:- 25 C 系列:VCNL3020 |
发布紧急采购，3分钟左右您将得到回复。