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参数资料
| 型号： | MK2069-04GILF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 标准包装： | 34 |
| 类型： | 时钟同步器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1254 (CN2011-ZH PDF) |
| 其它名称： | 800-1783 800-1783-5 800-1783-ND |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
6
MK2069-04
REV J 051310
Setting the VCXO PLL Loop Response
The VCXO PLL loop response is determined both by fixed
device characteristics and by variables set by the user. This
includes the values of RS, CS, CP and RSET as shown in the
External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by:
Where:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps
(see table on page 7)
KO = VCXO Gain in Hz/V
(see table on page 8)
SV Divider = 1,2,12 or 16
FV Divider = 1 to 4096
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
CS = Value of capacitor CS in loop filter in Farads
External VCXO PLL Components
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. A higher damping factor will create
less peaking in the passband and will further assure output
stability with the presence of system and power supply
noise. A damping factor of 4 will ensure a passband peak
less then 0.2 dB which may be required for network clock
wander transfer compliance. A higher damping factor may
also increase output clock jitter when there is excess digital
noise in the system application, due to the reduced ability of
the PLL to respond to and therefore compensate for phase
noise ingress.
Notes on setting the value of CP
As another general rule, the following relationship should be
maintained between components CS and CP in the loop
filter:
NBW(VCO PLL)
R
S
I
CP
×
K
O
×
2
π SV Divider
×
FV Divider
×
-----------------------------------------------------------------------------
=
NBW(VCO PLL)
f(Phase Detector)
20
---------------------------------------
≤
DF(VCLK)
R
S
2
------
I
CP
C
S
×
K
O
×
SV Divider
FV Divider
×
---------------------------------------------------------------
×
=
R
SET
C
P
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X1
15
16
X2
17
18
LFR
19
LF
20
ISET
25
26
27
28
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
M
K
2069
XTAL
C
L
C
L
R
S
C
S
Crystal Tuning
Capacitors
Refer to "Crystal Tuning Load
Capacitors" Section
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