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参数资料
| 型号： | MK2069-04GILF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 20/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SYNTHESIZER 56-TSSOP |
| 标准包装： | 34 |
| 类型： | 时钟同步器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1254 (CN2011-ZH PDF) |
| 其它名称： | 800-1783 800-1783-5 800-1783-ND |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
9
MK2069-04
REV J 051310
output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when
GR-1244-CORE compliance is not needed.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is
GR-1244-CORE compliant when used following a system synchronizer.
4) Lowering the phase detector frequency, by increasing the value of the RPV and/or RV dividers and the FV divider,
will lower the loop bandwidth and/or decrease the size of CS for the same damping factor.
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.idt.com/?app=calculators&source=support_menu.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the phase of
the input clock, which might occur when selecting a new
reference input through the use of an external clock
multiplexer.
The phase compensation circuit allows the VCXO PLL to
quickly lock to the new input clock phase without producing
extra clock cycles or clock wander, assuming the new clock
is at the same frequency.
Input pin CLR controls the phase compensation circuit. CLR
must remain high for normal operation. When used in
conjunction with an external multiplexer (MUX), CLR should
be brought low prior to MUX reselection, then returned high
after MUX reselection. This prevents the VCXO PLL from
attempting to lock to the new input clock phase associated
with the input clock.
When CLR is high, the VCXO PLL operates normally.
When CLR is low, the VCXO PLL charge pump output is
inactivated which means that no charge pump correction
pulses are provided to the loop filter. During this time, the
VCXO frequency is held constant by the residual charge or
voltage on the PLL loop filter, regardless of the input clock
condition. However, the VCXO frequency will drift over time,
eventually to the minimum pull range of the crystal, due to
leak-off of the loop filter charge. This means that CLR can
provide a holdover function, but only for a very short
duration, typically in milliseconds.
Upon bringing CLR high, the FV Divider is reset and begins
counting upon with the first positive edge of the new input
clock, and the charge pump is re-activated. By resetting the
FV Divider, the memory of the previous input clock phase is
removed from the feedback divider, eliminating the
generation of extra VCLK clock cycles that would occur if the
loop was to re-lock under normal means. Lock time is also
reduced, as is the generation of clock wander.
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips resulting.
When CLR is not used, the number of VCLK cycle slips can
be as high the FV Divider value.
TCLK is always locked to VCLK regardless of the state of
the CLR input.
Lock Detection
The MK2069-04 includes a lock detection feature that
indicates lock status of VCLK relative to the selected input
reference clock. When phase lock is achieved (such as
following power-up), the LD output goes high. When phase
lock is lost (such as when the input clock stops, drifts beyond
the pullable range of the crystal, or suddenly shifts in
phase), the LD output goes low.
The definition of a “locked” condition is determined by the
user. LD is high when the VCXO PLL phase detector error
is below the user-defined threshold. This threshold is set by
external components RLD and CLD shown in the Lock
Detection Circuit Diagram, below.
To help guard against false lock indications, the LD pin will
go high only when the phase error is below the set threshold
for 8 consecutive phase detector cycles. The LD pin will go
low when the phase error is above the set threshold for only
1 phase detector cycle.
The lock detector threshold (phase error) is determined by
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| MK2069-04GILFTR | 功能描述:时钟发生器及支持产品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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