参数资料
型号: MK2069-04GITR
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件页数: 17/21页
文件大小: 410K
代理商: MK2069-04GITR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
5
MK2069-04
REV J 051310
Application Information
The MK2069-04 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
RPV Divider = 1 or 8
RV Divider = 2 to 4097
Because the RPV divider inherently has a higher speed of
operation than the RV divider, the RPV divider should be set
to 8 when this factor is included in the RPV x RV divisor
combination.
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
f(VCLK)
FV Divider
RPV Divider
RV Divider
×
-------------------------------------------------------------------
f(ICLK)
×
=
f(VCLK)
fVCXO
()
SV Divider
-----------------------
=
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