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参数资料
| 型号： | MK2069-04GITR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 4/21页 |
| 文件大小： | 410K |
| 代理商： | MK2069-04GITR |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
12
MK2069-04
REV J 051310
Quartz Crystal
The MK2069-04 operates by phase-locking the VCXO
circuit to the input signal at the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the load capacitors connected to it. The
MK2069-04 incorporates variable load capacitors on-chip
which “pull” or change the frequency of the crystal. The
crystals specified for use with the MK2069-04 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2069-04 and the crystal.
Recommended Crystal Parameters:
Crystal parameters can be found in application note MAN05
on www.icst.com. Approved crystals can be found at
www.icst.com (search “crystal”).
Crystal Tuning Load Capacitors
The crystal traces should include pads for small capacitors
from X1 and X2 to ground, shown as CL in the External
VCXO PLL Components diagram on page 6. These
capacitors are used to center the total load capacitor
adjustment range imposed on the crystal. The load
adjustment range includes stray PCB capacitance that
varies with board layout. Because the typical telecom
reference frequency is accurate to less than 32 ppm, the
MK2069-04 may operate properly without these adjustment
capacitors. However, IDT recommends that these
capacitors be included to minimize the effects of variation in
individual crystals, including those induced by temperature
and aging. The value of these capacitors (typically 0-4 pF)
is determined once for a given board layout, using the
procedure described in MAN05.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed. Please
refer to the Recommended PCB Layout drawing on the
following page.
1) Each 0.01F decoupling capacitor (CD) should be
mounted on the component side of the board as close to the
VDD pin as possible. No via’s should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via. Distance of the ferrite chip and bulk
decoupling from the device is less critical.
2) The loop filter components must also be placed close to
the CHGP and VIN pins. CP should be closest to the device.
Coupling of noise from other system signal traces should be
minimized by keeping traces short and away from active
signal traces. Use of vias should be avoided.
3) The external crystal should be mounted as close the
device as possible, on the component side of the board.
This will keep the crystal PCB traces short which will
minimize parasitic load capacitance on the crystal and as
well as noise pickup. The crystal traces should be spaced
away from each other and should use minimum trace width.
There should be no signal traces near the crystal or the
traces. Also refer to the Optional Crystal Shielding section
that follows.
4) To minimize EMI the 33
series termination resistor, if
needed, should be placed close to the clock output.
5) All components should be on the same side of the board,
minimizing vias through other signal layers (the ferrite bead
and bulk decoupling capacitor may be mounted on the
back). Other signal traces should be routed away from the
MK2069-04. This includes signal traces on PCB traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
6) Because each input selection pin includes an internal
pull-up device, those inputs requiring a logic high state (“1”)
can be left unconnected. The pins requiring a logic low state
(“0”) can be grounded.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2 are
sensitive to noise pickup. In applications that especially
sensitive to noise, such as SONET or G-Bit ethernet
transceivers, some or all of the following crystal shielding
techniques should be considered. This is especially
important when the MK2069-04 is placed near high speed
logic or signal traces.
The following techniques are illustrated on the
Recommended PCB Layout drawing.
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