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参数资料
| 型号： | MK53DX256ZCMD10R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封装： | 13 X 13 MM, MAPBGA-144 |
| 文件页数： | 24/82页 |
| 文件大小： | 1124K |
| 代理商： | MK53DX256ZCMD10R |
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Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
—
23.99
—
MHz
Mid range (DRS=01)
1464 × ffll_ref
—
47.97
—
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
—
71.99
—
MHz
High range (DRS=11)
2929 × ffll_ref
—
95.98
—
MHz
Jcyc_fll
FLL period jitter
—
TBD
ps
Jacc_fll
FLL accumulated jitter of DCO output over a 1s
time window
—
TBD
ps
tfll_acquire
FLL target frequency acquisition time
—
1
ms
PLL
fvco
VCO operating frequency
48.0
—
100
MHz
Ipll
PLL operating current
PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
—
1060
—
A
Ipll
PLL operating current
PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
—
600
—
A
fpll_ref
PLL reference frequency range
2.0
—
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
fvco = 48 MHz
fvco = 100 MHz
—
120
50
—
ps
Jacc_pll
PLL accumulated jitter over 1s (RMS)
fvco = 48 MHz
fvco = 100 MHz
—
1350
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
0.15 +
1075(1/
fpll_ref)
ms
1. The startup time is defined as the time between the IRC being enabled, either by the MCG or by the IRCLKEN bit being
set, and the first edge of the internal reference clock.
2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(
Δfdco_t) over voltage and temperature should be considered.
Peripheral operating requirements and behaviors
K53 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
30
Preliminary
Freescale Semiconductor, Inc.
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