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参数资料
| 型号： | MK74CG117FIT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 2/5页 |
| 文件大小： | 69K |
| 代理商： | MK74CG117FIT |
MDS 74CG117 D
2
Revision 041502
Integrated Circuit Systems 525 Race Street. San Jose CA95126 (408)295-9800tel www.icst.com
MK74CG117
16 Output Low Skew Clock Generator
Number
Name
Type Description
1, 15, 16, 24, 30, 35, 36, 45, 46
VDD
P
Connect to VDD.
2
X1/ICLK
XI
Connect to a crystal or input clock
3
X2
XO
Connect to a crystal, or leave unconnected for clock input.
4, 5, 21, 29, 44
NC
-
No Connect. Nothing is connected internally to these pins.
6, 7, 11, 12, 19, 20, 27, 28, 40, 41
GND
P
Connect to ground.
8, 10, 48
S2, S1, S0
I
Multiplier select pins. See Table 2.
9
REF
O
Crystal oscillator buffered reference clock output.
13, 14, 17, 18
CLK1-4
O
Clocks 1-4. Can be either full or half speed per Table 1.
22, 23, 25, 26, 31, 32, 33, 37
CLK5-12
O
Clock outputs 5-12. At full (1X) speed unless tristated per Table 1.
34, 39
M0, M1
I
Mode Select pins. Selects tri-state or speed of outputs per Table 1.
38, 42, 43, 47
CLK13-16
O
Clocks 13-16. Can be either full or half speed per Table 1.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
43
42
47
44
45
46
48
REF
GND
X2
VDD
NC
S1
S2
X1/ICLK
NC
CLK2
GND
CLK1
GND
S0
CLK16
CLK15
VDD
NC
VDD
15
22
23
16
17
18
19
20
21
24
25
26
27
28
30
29
33
31
32
38
37
36
35
34
39
40
41
M0
VDD
CLK12
GND
CLK14
CLK11
VDD
GND
M1
NC
CLK10
VDD
CLK9
CLK13
CLK6
NC
GND
CLK3
VDD
GND
VDD
CLK5
VDD
CLK4
CLK7
GND
CLK8
GND
For proper operation, the device should have 0.1 F and 0.01 F capacitors connected between each VDD and
GND. If a crystal is used, it should be fundamental mode, parallel resonant. The oscillator has internal caps that
provide the proper load for a crystal with CL = 18 pF. For other values of CL, the formula 2*(CL-18) gives the value
of each capacitor that should be connected between X1 and ground and X2 and ground.
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