参数资料
型号: MK74CG117FIT
元件分类: 时钟产生/分配
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO48
封装: SSOP-48
文件页数: 3/5页
文件大小: 69K
代理商: MK74CG117FIT
MDS 74CG117 D
3
Revision 041502
Integrated Circuit Systems 525 Race Street. San Jose CA95126 (408)295-9800tel www.icst.com
MK74CG117
16 Output Low Skew Clock Generator
M1 M0
Mode
At CLK (1X)
At CLK/2 (0.5X)Max Output Freq
0
All outputs tri-stated Z
Z
--
0
1
12 at 1X, 4 at 0.5X
CLK1-12
CLK13-16
83.3 MHz
1
0
8 at 1X, 8 at 0.5X
CLK5-12
CLK1-4, 13-16
83.3 MHz
1
16 outputs at 1X
CLK1-16
None
100 MHz
Table 1. Tri-state and Mode Select
S2 S1 S0
Input
Multiplier CLK Out
Comments
0
33 - 50
0.5
16.5 - 25
Divider only; no PLL
0
1
20 - 50
1
20 - 50
PLL
0
1
0
16 - 40
1.25
20 - 50
PLL
0
1
10 - 50
2
20 - 100
PLL
1
0
8 - 40
2.5
20 - 100
PLL
1
0
1
8 - 30
3.333
26.7 - 100
PLL
1
0
8 - 25
4
32 - 100
PLL
1
8 - 20
5
40 - 100
PLL
Table 2. Multiplier Selections (Input and CLK Frequencies in MHz)
Power Dissipation, Termination, and
Operating Frequency
As with all clock drivers, the power dissipated by the
MK74CG117 is affected by the external loading on the
output pins. This consists of the capacitance of the
load that is being driven, as well as the PC board trace
itself. Since this capacitance must be charged and
discharged with each cycle of the output clock, as the
frequency goes up. so does the power required.
Operating below the specified maximum output clock
frequency shown in Table 2 will keep the MK74CG117
power dissipation within acceptable limits.
External series termination resistors must be used in
series with each output. These resistors serve two
purposes: The first is to match the source impedance
to the line (PC board trace) that is being driven. This
will minimize reflections that cause non-linear
transitions on the output clock waveform. The output
impedance of the MK74CG117 is approximately 20
;
assuming a 50
line, then a 33 resistor should be
used at each output as shown in Figure 1.
MK74CG117
Output
To load
Figure 1. External Termination
33
Another reason for using the external resistors is to
reduce the power dissipation of the MK74CG117 at high
output clock speeds.
As speeds rise, the limiting factor in device operation
becomes the power generated by having a large number
of drivers in one package. Using the external termination
resistors reduces the power dissipated within the
device, allowing output frequencies up to 100 MHz.
Note that the maximum operating frequency of the
MK74CG117 is determined by
the Mode selected from Table 1
and the Multiplier selected from
Table 2. For output frequencies
above 83.3 MHz, all 16 outputs
must be at the same frequency
(M1=M0=1).
When operating with a
combination of 1X and 0.5X
outputs, the output frequency
cannot exceed 83.3 MHz.
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