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参数资料
| 型号： | MK74CG117FIT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 4/5页 |
| 文件大小： | 69K |
| 代理商： | MK74CG117FIT |
MDS 74CG117 D
4
Revision 041502
Integrated Circuit Systems 525 Race Street. San Jose CA95126 (408)295-9800tel www.icst.com
MK74CG117
16 Output Low Skew Clock Generator
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
0.5
VDD+0.5
V
Ambient Operating Temperature
-40
85
C
Soldering Temperature
Max of 10 seconds
260
C
Storage Temperature
-65
150
C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.14
3.3
3.47
V
Input High Voltage, VIH, ICLK
pin 2
VDD-1
VDD/2
V
Input Low Voltage, VIL, ICLK
pin 2
VDD/2
1
V
Output High Voltage
IOH=-8mA
VDD-0.4
V
Output High Voltage
IOH=-12mA
2
V
Output Low Voltage, 3.3 V
IOL=12mA
0.4
V
Operating Supply Current, IDD, at 50 MHz
No Load
63
mA
Short Circuit Current
Each output
±35
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Clock Frequency
Refer to Table 2
Input Crystal Frequency
Except when S2=S1=1
8
20
MHz
Output Clock Frequency (See Tables 1, 2)
M1=M0=1
100
MHz
Output Clock Rise Time
0.8 to 2.0V. Note 2
1.5
2
ns
Output Clock Fall Time
2.0 to 0.8V. Note 2
1.5
2
ns
Output Clock Rising Edge Skew
VDD = 3.3 V. Note 3
150
250
ps
Output Clock Duty Cycle
At VDD/2
45
50
55
%
Absolute Clock Period Jitter, except REF
VDD = 3.3 V
±300
ps
Absolute Clock Period Jitter, REF
VDD = 3.3V
±500
ps
Maximum load per total of 16 outputs, with
100MHz output clock
240
pF
33
termination. Note 4
83.3MHz output clock
320
pF
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device.
Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device
reliability.
2. Based upon characterization data. Specified at VDD/2, with a 33
series termination resistor and 15 pF capacitor
to ground.
3. Between any two outputs with equal loading.
4. Additional load may be driven with the addition of an external heat sink. Contact ICS for details.
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