参数资料
型号: ML2021CP
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 模拟传输电路
中文描述: TELECOM-LINE EQUALIZER, PDIP16
封装: PLASTIC, DIP-16
文件页数: 11/11页
文件大小: 93K
代理商: ML2021CP
PRODUCT SPECIFICATION
ML2021
REV. 1.1.1 3/19/01
9
high. The LATI pulse must occur when SCK is low. A new
data word can be loaded into the shift register without dis-
turbing the existing data word in the latch.
The parallel outputs of the latch control the lter response
curves. The order of the data word bits in the latch is shown
in Figure 7.
Note that bit 0 is the rst bit of the data word clocked into the
shift register.
The device has the capability to read out the data word stored
in the latch. This is done by parallel loading the data from
the latch back into the shift register when the latch signal,
LATO, is high. The LATO pulse must occur when SCK is
low. Then, the data word can be shifted out of the register
serially to the output, SOD, on falling edges of the shift
clock, SCK.
The loading and reading of the data word can be done con-
tinuously or in bursts. Since the shift register and latch cir-
cuitry inside the device is static, there are no minimum
frequency requirements on the clocks or data pulses. How-
ever, there is some coupling of the digital signals in the ana-
log section. If this coupling is undesirable, the data can be
clocked in bursts during non critical intervals, or the data rate
can be done at a frequency outside the analog frequency
range.
The clocks used to shift and latch data (SCK, LATI, LATO)
are not related internally to the master clock and can occur
asynchronous to CLK.
Figure 6. Serial Timing
Figure 7. 14-Bit Latch
SCK
012
34
5
6
789
10
11
12
13
012
34
5
a) LOAD
b) READ
6
7
8
9
10
11
12
13
SID
BP
H0
H1
H2
H3
B0
B1
B2
B3
S0
S1
S2
S3
NL/L
LATI
LATO
SOD
SCK
SID
LATI
LATO
SOD
BP
H0
H1
H2
H3
B0
B1
B2
B3
S0
S1
S2
S3
NL/L
S3
S2
S1
13
12
11
10
9
8
7
6
5
43210
S0
B3
B2
B1
B0
H3
H2
H1
H0
SLOPE
BANDWIDTH
HEIGHT
BYPASS
FUNCTION
BIT NUMBER
BP
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