参数资料
型号: ML2021CP
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 模拟传输电路
中文描述: TELECOM-LINE EQUALIZER, PDIP16
封装: PLASTIC, DIP-16
文件页数: 4/11页
文件大小: 93K
代理商: ML2021CP
ML2021
PRODUCT SPECIFICATION
2
REV. 1.1.1 3/19/01
Pin Description
Absolute Maximum Ratings1
Operating Conditions
Name
Function
CLKSEL
Clock select input. This pin selects the frequency of the CLK input. If CLK is 1.536 MHz, set
CLKSEL = 1. If CLK is 1.544 MHz, set CLKSEL = 0. Pin has an internal pullup resistor to VCC.
SID
Serial input data. Digital input that contains serial data word which controls the filter frequency
response setting.
LATO
Output latch clock. Digital input which loads the data word back into the shift register from the latch.
SCK
Shift clock. Digital input which shifts the serial data on SID into the shift register on rising edges and
out onto SOD on falling edges.
SOD
Serial output data. Digital output of the shift register.
CLK
Master clock input. Digital input which generates clocks for the switched capacitor filters.
Frequency can be either 1.544 MHz or 1.536 MHz.
GND
Digital ground. 0 volts. All digital inputs and output are referenced to this ground.
LATI
Input latch clock. Digital input which loads data from the shift register into the latch.
VSS
Negative supply. –5volts ±10%.
VIN
Analog input.
AGND
Analog ground. 0 volts. Analog input and output are referenced to this ground.
VOUT
Analog output.
PDN
Powerdown input. When PDN = 1, device is in powerdown mode. When PND = 0, device is in normal
operation. This pin has an internal pulldown resistor to GND.
VCC
Positive supply. 5 volts ± 10%
Parameter
Min.
Max.
Units
Supply Voltage
VCC
VSS
+6.5
-6.5
V
AGND with respect to GND
±0.5
V
Analog Input and Output
VSS –0.3
VCC +0.3
V
Digital Input and Outputs
GND –0.3
VCC +0.3
V
Input Current Per Pin
±25
mA
Power Dissipation
750
mW
Storage Temperature Range
-65
+150
°C
Lead Temperature (Soldering, 10 sec)
300
°C
Parameter
Min.
Max.
Units
Temperature Range2
ML2021CX
ML2021IX
0
-40
70
85
°C
Supply Voltage
VCC
VSS
4
-4
6
-6
V
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