参数资料
型号: ML2021CP
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 模拟传输电路
中文描述: TELECOM-LINE EQUALIZER, PDIP16
封装: PLASTIC, DIP-16
文件页数: 2/11页
文件大小: 93K
代理商: ML2021CP
ML2021
PRODUCT SPECIFICATION
10
REV. 1.1.1 3/19/01
Powerdown Mode
A powerdown mode can be selected with pin PDN. When
PDN = 1, the device is powered down. In this state, the power
consumption is reduced by removing power from the analog
section and forcing the analog output, VOUT, to a high
impedance state. While the device is in power down mode,
the digital section is still functional and the current data word
remains stored in the latch. The master clock, CLK, can
be left active or removed during powerdown mode. When
PDN = 0, the device is in normal operation.
Power Supplies
The digital section inside the device is powered between
VCC and GND, or 5 volts. The analog section is powered
between VCC and VSS, or ±5 volts. The analog section uses
AGND as the reference point.
GND and AGND are totally isolated inside the device to
minimize coupling from the digital section into the analog
section. Typically this is less than 100 V. However, ANGD
and GND should be tied together physically near the device
and close to the common power supply ground connection.
The power supply rejection of VCC and VSS to the analog
output is greater than –60dB at 1 kHz, typically. If decou-
pling of the power supplies is still necessary in a system,
VCC and VSS should be decoupled with respect to AGND.
Applications
Figure 8. Typical Serial Interface
Figure 9. Controlling Multiple ML2021 and ML2004 With
Only 3 Digital Lines Using One Long Data Word
ML2004
LOG GAIN/ATTEN
ML2021
EQUALIZER
VIN
VOUT
P
VIN
SID
SCK
LA
TI
SID
SCK
LA
TI
VOUT
P
ML2021 OR ML2004
VIN
VOUT
SID
SCK
LA
TI
SOD
ML2021 OR ML2004
VIN
VOUT
SID
SCK
LA
TI
SOD
ML2021 OR ML2004
VIN
VOUT
SID
SCK
LA
TI
SOD
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相关代理商/技术参数
参数描述
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