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参数资料
| 型号： | ML60851ETB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 2/85页 |
| 文件大小： | 387K |
| 代理商： | ML60851ETB |
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FEDL60851E-01
OKI Semiconductor
ML60851E
9/84
End Point 0 Transmit FIFO (EP0TXFIFO)
Read address
—
Write address
C0h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP0 Transmit data (W)
EP0 transmit data can be written in by writing to the address C0h. The receive data from the host in the data stage
during a control read transfer is stored in EP0TXFIFO. When the ML60851E issues an EP0 transmit packet ready
interrupt request, the local MCU writes the transmit data to the address C0h. It is possible to write the packet data
successively by writing continuously.
The EP0 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP0.
2. When a setup packet is received.
End Point 1 Transmit FIFO (EP1TXFIFO)
Read address
—
Write address
C1h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP1 Transmit data (W)
The EP1 transmit data can be written in by writing to the address C1h. When EP1 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851E
issues an EP1 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP1 is set as ‘Receive’, all accesses to this address will be
invalid.
The EP1 transmit FIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP1.
2. When the local MCU writes a “1” in the EP1FIFO clear bit (CLRFIFO(1)).
Even when a DMA write with a 16-bit width is made in EP1TXFIFO, the address is A7:A0 = 41h.
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