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参数资料
| 型号： | ML60851ETB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 8/85页 |
| 文件大小： | 387K |
| 代理商： | ML60851ETB |
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FEDL60851E-01
OKI Semiconductor
ML60851E
15/84
End Point Packet Ready Register (PKTRDY)
This register indicates whether or not the preparations for reading out or writing in a packet data have been
completed. In addition, this register is also used for controlling the handshake packet (ACK/NAK)
Read address
C8h
Write address
48h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
After a bus reset
0
Definition
0
This register in conjunction with INTENBL register is used for controlling the read/write operation of
ML60851E’s transmit and receive FIFOs. The interrupt generation and disassertion of ML60851E is closely
related to the bits in PKTRDY register and the corresponding fields in INTENBL register.
During normal operation, when ML60851E is receiving data from the host, the data packet received succussfully
without any errors will be stored in the corresponding Rx FIFO of ML60851E, at which point ML60851E will
automatically assert its Receive Packet Ready bit and generate an interrupt cause. At this time if interrupt for the
particular endpoint has been enabled in the INTENBL register, the corresponding interrupt status bit in register
INTSTAT will be asserted and an interrupt will be generated.
In a transmit operation, when ML60851E is sending data to the host, an ACK packet received from the host in
response to succussful transmission of a packet will cause ML60851E to automatically deassert (set to “0”) the
corresponding endpoint’s transmit packet ready bit and hence, generate an interrupt cause. To transmit subsequent
packets from this same end point, the local MCU sets the corresponding transmit packet ready bit after completion
of interrupt servicing (such as writing data in the corresponding transmit FIFO, etc.).
Bit D3 is fixed at “0”, and even if a “1” is written in this bit, that write operation will be invalid.
The operations of the different bits of PKTRDY are described in detail below.
Please note the R/Reset and R/Set notation used above. R/Reset means: the bit field can be read by the local
MCU/and it is Reset (to ‘0’) when a “1” is written to it. The R/Set means: the bit field can be read by the local
MCU/and it is Set (to ‘1’) when a 1 is written to it.
EP0 Receive packet ready (R/Reset)
EP1 Receive packet ready (R/Reset)
EP2 Receive packet ready (R/Reset)
EP0 Transmit packet ready (R/Set)
EP1 Transmit packet ready (R/Set)
EP2 Transmit packet ready (R/Set)
EP3 Transmit packet ready (R/Set)
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