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参数资料
| 型号： | ML60851ETB |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件页数： | 3/85页 |
| 文件大小： | 387K |
| 代理商： | ML60851ETB |
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FEDL60851E-01
OKI Semiconductor
ML60851E
10/84
End Point 2 Transmit FIFO (EP2TXFIFO)
Read address
—
Write address
C2h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP2 Transmit data (W)
EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk transmission
(BULK IN), the local MCU should write the transmit data in EP2TXFIFO when the ML60851E issues an EP2
packet ready interrupt request. It is possible to write the packet data successively by writing continuously. When
the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be invalid.
The EP2 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP2.
2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).
End Point 3 Transmit FIFO (EP3TXFIFO)
Read address
—
Write address
C3h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP3 Transmit data (W)
EP3 transmit data can be written in by writing to the address C3h. The local MCU should write the transmit data in
EP3TXFIFO when ML60851E issues an EP3 packet ready interrupt request. It is possible to write the packet data
successively by writing continuously.
The EP3 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP3.
2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).
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