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参数资料
| 型号： | MMA6556KW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 46/53页 |
| 文件大小： | 0K |
| 描述： | IC ACCELEROMETER X AXIS 16QFN |
| 标准包装： | 75 |
| 轴： | X |
| 加速范围： | ±120g |
| 灵敏度： | 16 LSB/g |
| 电源电压： | 3.13 V ~ 5.25 V |
| 输出类型： | SPI |
| 接口： | SPI |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-QFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（6x6） |
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4.3
Acceleration Data Transfers
12-Bit Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ‘1’,
and bit D[3] of the SPI command message is set to a logic ‘1’. The Axis Selection bit (AX) selects the type of acceleration data
requested, as shown in Table 28 .
Table 28. Acceleration Data Request
Axis Selection Bit (AX)
0
1
Data Type
Acceleration Data
Invalid Accel Request
To verify that the device is configured as expected, each acceleration data request includes the configuration information which
impacts the output data. The requested configuration is compared against the data programmed in the writable register block.
Details are shown in Table 29 .
Table 29. Acceleration Data Request Configuration Information
Programmable Option
Raw or Offset Cancelled Data
Signed or Unsigned Data
Arming Function or PCM Output
Command Message Bit
OC
SD
ARM
Writable Register Information
DEVCFG[7] (OC)
DEVCFG[4] (SD)
DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1])
If the data listed in Table 29 does not does not match, an Acceleration Data Request Mismatch failure is detected and no ac-
celeration data is transmitted. Reference Section 4.5.3.1 .
Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the accel-
eration data request command must be an odd number.
Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met:
? The DEVINIT bit in the DEVSTAT register is not set
? The DEVRES bit in the DEVSTAT register is not set
? The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5 )
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1 )
? No Self Test Error is present (reference Section 4.5.5.2 )
? No Offset Monitor Error is present for the requested channel (reference Section 4.5.6 )
If the above conditions are met, the device responds with a “valid acceleration data request” response as shown in Table 27 .
Otherwise, the device responds as specified in Section 4.5 .
4.4
Register Access Operations
Two types of register access operations are supported; register write, and register read. Register access operations are initi-
ated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by
the Access Selection bit (AX) of the command message.
Access Selection Bit (AX)
0
1
Operation
Register Read
Register Write
Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access
operation must be an odd number.
MMA655x
Sensor
46
Freescale Semiconductor, Inc.
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| MMA6556KWR2 | 功能描述:加速计 - 板上安装 X-AXIS 120G RoHS:否 制造商:Murata 传感轴:Double 加速:12 g 灵敏度: 封装 / 箱体: 输出类型:Analog 数字输出 - 位数:11 bit 电源电压-最大:5.25 V 电源电压-最小:4.75 V 电源电流:4 mA 最大工作温度:+ 125 C 最小工作温度:- 40 C |
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