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| 型号： | MMA6556KW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/53页 |
| 文件大小： | 0K |
| 描述： | IC ACCELEROMETER X AXIS 16QFN |
| 标准包装： | 75 |
| 轴： | X |
| 加速范围： | ±120g |
| 灵敏度： | 16 LSB/g |
| 电源电压： | 3.13 V ~ 5.25 V |
| 输出类型： | SPI |
| 接口： | SPI |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-QFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（6x6） |
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4.5.3.2 Invalid Register Request
The following conditions result in an “Invalid Register Request” error:
? An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1 , Table 3 ). Attempts to
write to registers $07, $09, $0D, $0F, $11, & $13, $18, $19, $1A and $1B will result in an error.
? An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set
? This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
? An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1 , Table 3 ). Attempts to
read registers $07, $09, $0D, $0F, $11, & $13, $18, $19, $1A and $1B will result in an error.
The device responds to an Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30 .
4.5.4
Device Reset Indications
If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.11 , the device will respond to ac-
celeration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT
bit is cleared automatically when device initialization is complete (Reference t OP in Section 2.6 ). The DEVRES bit is cleared on
a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT
or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.
4.5.5
Internal Error
The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:
? OTP CRC Failure
? Writable Register CRC Failure
? Self Test Error
? Invalid internal logic states
4.5.5.1 CRC Error
If the IDE bit is set in the DEVSTAT register due to one or more of the following errors, the device will respond to acceleration
data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register.
? An OTP Shadow Register CRC failure as described in Section 3.2
? A Writable Register CRC failure as described in Section 3.2
The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output
is not affected by the CRC error.
If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only
be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register.
If the CRC error is in the OTP shadow register array, the error cannot be cleared.
Register operations will be executed as specified in Section 4.4 .
4.5.5.2 Self Test Error
If the IDE bit is set in the DEVSTAT register due to a Self Test activation failure, the device will respond to acceleration data
requests with a “Self Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be
updated on Acceleration Data Request commands if a Self Test Error is detected. The PCM output is not affected by the Self Test
Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure
is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set.
Register operations will be executed as specified in Section 4.4 .
4.5.6
Offset Monitor Error
If an offset monitor error is present as described in Section 3.8.5 , the OFFSET bit in the DEVSTAT register will be set. The
device will respond to an acceleration request with an “Internal Error Present” response until the OFFSET bit is cleared in the
DEVSTAT register. The arming function will not be updated. Once the error condition is removed, the OFFSET bit in the DEVSTAT
register will remain set until a read of the DEVSTAT register occurs.
The PCM output is not affected by the offset monitor over range condition.
Register operations will be executed as specified in Section 4.4 .
MMA655x
Sensor
Freescale Semiconductor, Inc.
49
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| MMA6556KWR2 | 功能描述:加速计 - 板上安装 X-AXIS 120G RoHS:否 制造商:Murata 传感轴:Double 加速:12 g 灵敏度: 封装 / 箱体: 输出类型:Analog 数字输出 - 位数:11 bit 电源电压-最大:5.25 V 电源电压-最小:4.75 V 电源电流:4 mA 最大工作温度:+ 125 C 最小工作温度:- 40 C |
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