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Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS V
SOT-223 for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Available in 12 mm Tape & Reel
Use MMFT3055VLT1 to order the 7 inch/1000 unit reel
Use MMFT3055VLT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
60
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR
60
Vdc
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 20
Vdc
Vpk
Drain Current – Continuous
Drain Current – Continuous @ 100
°C
Drain Current – Single Pulse (tp ≤ 10 s)
ID
IDM
1.5
1.2
5.0
Adc
Apk
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material
Derate above 25
°C
PD
2.1
1.7
0.94
6.3
Watts
mW/
°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 )
EAS
58
mJ
Thermal Resistance
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material
– Junction to Ambient on min. Drain pad on FR–4 bd material
R
θJA
R
θJA
R
θJA
70
88
159
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
Order this document
by MMFT3055VL/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
TM
MMFT3055VL
TMOS POWER FET
1.5 AMPERES
60 VOLTS
RDS(on) = 0.140 OHM
D
S
G
CASE 318E–04, Style 3
TO–261AA
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Motorola, Inc. 1996