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参数资料
| 型号： | MP1531DQ-LF-Z |
| 厂商： | MONOLITHIC POWER SYSTEMS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 0.65 A SWITCHING REGULATOR, 300 kHz SWITCHING FREQ-MAX, QCC16 |
| 封装： | 3 X 3 MM, ROHS COMPLIANT, MO-220VEED-4, QFN-16 |
| 文件页数： | 2/12页 |
| 文件大小： | 287K |
| 代理商： | MP1531DQ-LF-Z |
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
MP1531 Rev. 1.3
www.MonolithicPower.com
10
12/4/2009
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2009 MPS. All Rights Reserved.
The output filter zero is given in hertz by:
2
C
R
2
1
f
ESR
FILTERZERO
×
π
×
=
Where RESR is the equivalent series resistance
of the output capacitor.
With all boost regulators the right half plane
zero (RHPZ) is given in hertz by:
1
L
I
2
V
f
LOAD
MAIN
2
MAIN
IN
RHPZ
×
π
×
=
Error Amplifier Compensation
To stabilize the feedback loop dynamics the
error amplifier compensation is as follows:
3
C
10
2
1
f
6
1
POLE
×
π
×
≈
3
C
3
R
2
1
f
1
ZERO
×
π
=
Where R3 and C3 are part of the compensation
network in Figure 3. A good start is 5.6k and
10nF. This combination gives about 70° of
phase margin and bandwidth of about 35KHz
for most load conditions. Increasing R3 and/or
reducing C3 increases the loop bandwidth and
improves the load transient.
Linear Regulator Compensation
The positive or negative regulated voltages of
two linear regulators are controlled by a
transconductance amplifier and a P-channel or
N-Channel pass transistor respectively. The DC
gain of either LDO is approximately 100dB with
a slight dependency on load current. The output
capacitor (CLDO) and resistance load (RLOAD)
make-up the dominant pole.
LDO
LOAD
1
LDOPOLE
C
R
2
1
f
×
π
×
=
The pass transistor’s internal pole is about
10Hz to 30Hz. To compensate for the two pole
system and add more phase and gain margin, a
lead-lag resistor capacitor network is necessary.
For the positive linear regulator:
() 7
C
8
R
||
9
R
10
R
2
1
f
1
POSPOLE
×
+
×
π
×
=
() 7
C
9
R
10
R
2
1
f
1
POSZERO
×
+
×
π
×
=
For the negative linear regulator:
() 9
C
5
R
||
7
R
6
R
2
1
f
1
NEGPOLE
×
+
×
π
×
=
() 9
C
7
R
6
R
2
1
f
1
NEGZERO
×
+
×
π
×
=
fPOSPOLE1 and fNEGPOLE1 are necessary to cancel
out the zero created by the equivalent series
resistance (RLDOESR) of the output capacitor.
LDO
LDOESR
LDOZERO
C
R
2
1
f
×
π
×
=
For component values shown in Figure 3 a 10
and 56pF RC network gives about 45° of phase
margin and a bandwidth of about 35KHz on
both regulators.
Layout Considerations
Careful PC board layout is important to
minimize ground bounce and noise. First, place
the main boost converter inductor, output diode
and output capacitor as close to the SW and
PGND pins as possible with wide traces. Then
place ceramic bypass capacitors near IN, IN2
and IN3 pins to the PGND pin. Keep the
charge-pump circuitry close to the IC with wide
traces. Locate all FB resistive dividers as close
to their respective FB pins as possible.
Separate GND and PGND areas and connect
them at one point as close to the IC as possible.
Avoid having sensitive traces near the SW node
and high current lines. Refer to the MP1531
demo board for an example of proper board
layout.
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