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| 型号： | MPC5123VY400B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PBGA516 |
| 封装： | 27 X 27 MM, ROHS COMPLIANT, PLASTIC, TFBGA-516 |
| 文件页数： | 19/86页 |
| 文件大小： | 1266K |
| 代理商： | MPC5123VY400B |
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MPC5121E/MPC5123 Data Sheet, Rev. 1
Electrical and Thermal Characteristics
Freescale Semiconductor
26
3.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
Sys PLL VCO frequency1
fVCOsys
400
—
800
MHz
O3.3
Sys PLL VCO output jitter (Dj),
peak to peak / cycle
fVCOjitterDj
—
40
ps
O3.4
Sys PLL VCO output jitter (Rj), rms
1 sigma
fVCOjitterRj
—
12
ps
O3.5
Sys PLL relock time - after power
up 3
tlock1
—
200
μsO3.6
Sys PLL relock time - when power
was on4
tlock2
—
170
μsO3.7
1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
2 This represents total input jitter - short term and long term combined. Two different types of jitter can exist
on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic
jitter is passed into and through the PLL to the internal clock circuitry.
3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence.
4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled
and subsequently re-enabled during sleep modes.
Table 15. e300 PLL Specifications
Characteristic
Sym
Min
Typical
Max
Unit
SpecID
e300 frequency1
1 The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies,
CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies in Table 16.
fcore
50
—
400
MHz
O4.1
e300 PLL VCO frequency1
fVCOcore
400
—
800
MHz
O4.3
e300 PLL input clock frequency
fCSB_CLK
50
—
200
MHz
O4.4
e300 PLL input clock cycle time
tCSB_CLK
5
—
20
ns
O4.5
e300 PLL relock time2
2 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep modes.
tlock
—
200
μsO4.6
Table 14. System PLL Specifications
Characteristic
Sym
Min
Typical
Max
Unit
SpecID
Preliminary
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5123VY400BR | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core |
| MPC5123YVY300B | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Advance Information |
| MPC5123YVY300BR | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Advance Information |
| MPC5123YVY400B | 功能描述:微处理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC5123YVY400BR | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core |
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