参数资料
型号: MPC5200CVR400
厂商: Freescale Semiconductor
文件页数: 21/80页
文件大小: 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
标准包装: 40
系列: MPC52xx
核心处理器: 603e G2 LE
芯体尺寸: 32-位
速度: 400MHz
连通性: CAN,EBI/EMI,以太网,I²C,IrDA,J1850,SPI,UART/USART,USB
外围设备: AC'97,DMA,I²S,POR,PWM,WDT
输入/输出数: 56
程序存储器类型: 外部程序存储器
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 272-BBGA
包装: 托盘
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
28
3.3.7
Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable
Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and
MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data size in Byte
tPCIck = PCI clock period
tIPBIck = IPBI clock period
Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
3.3.7.1
Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym
Description
Min
Max
Units
Notes
SpecID
tCSA
PCI CLK to CS assertion
-
1.8
ns
A7.1
tCSN
PCI CLK to CS negation
-
1.8
ns
A7.2
t1
CS pulse width
(2+WS)*tPCIck
ns
1
A7.3
t2
ADDR valid before CS assertion
tIPBIck
tPCIck
ns
A7.4
t3
ADDR hold after CS negation
tIPBIck
-ns
2
A7.5
t4
OE assertion before CS assertion
-
0.4
ns
A7.6
t5
OE negation before CS negation
-
0.4
ns
A7.7
t6
RW valid before CS assertion
tPCIck
-ns
A7.8
t7
RW hold after CS negation
tIPBIck
-ns
A7.9
t8
DATA output valid before CS assertion
tIPBIck
-
ns
A7.10
t9
DATA output hold after CS negation
tIPBIck
-
ns
A7.11
t10
DATA input setup before CS negation
2.8
-
ns
A7.12
t11
DATA input hold after CS negation
0
(DC+1)*tPCIck
ns
A7.13
t12
ACK assertion after CS assertion
tPCIck
-ns
3
A7.14
t13
ACK negation after CS negation
-
tPCIck
ns
3
A7.15
PCI CLK
IPBI CLK
tIPBIck
tPCIck
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