参数资料
型号: MPC5200CVR400
厂商: Freescale Semiconductor
文件页数: 70/80页
文件大小: 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
标准包装: 40
系列: MPC52xx
核心处理器: 603e G2 LE
芯体尺寸: 32-位
速度: 400MHz
连通性: CAN,EBI/EMI,以太网,I²C,IrDA,J1850,SPI,UART/USART,USB
外围设备: AC'97,DMA,I²S,POR,PWM,WDT
输入/输出数: 56
程序存储器类型: 外部程序存储器
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 272-BBGA
包装: 托盘
MPC5200 Data Sheet, Rev. 4
System Design Information
Freescale Semiconductor
72
Figure 52. Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down
sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1
Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads
will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance
state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must
power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4
V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection
clamp diodes.
The recommended power up sequence is as follows:
Use one microsecond or slower rise time for all supplies.
1.5V
2.5V
3.3V
0
DC
Pow
er
Supply
V
o
ltage
VDD_IO,
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
VDD_CORE,
PLL_AVDD
Note:
1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than
0.4 V at any time, including power-up.
2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM
up to 0.9 V then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM,
VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.
4. Use 1 microsecond or slower rise time for all supplies.
1
2
Time
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