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参数资料
| 型号： | MPC5534MZQ80 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 12/60页 |
| 文件大小： | 0K |
| 描述： | MCU 1MB FLASH 80MHZ 324-PBGA |
| 标准包装： | 60 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z6 |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，以太网，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 192 |
| 程序存储器容量： | 1MB（1M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 64K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 324-BBGA |
| 包装： | 托盘 |
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MPC5534 Microcontroller Data Sheet, Rev. 6
Overview
Freescale Semiconductor
2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The MPC5534 has a single-level memory hierarchy consisting of 64-kilobytes (KB) on-chip SRAM and
one megabyte (MB) of internal flash memory. Both the SRAM and the flash memory can hold instructions
and data. The external bus interface (EBI) supports most standard memories used with the MPC5xx family.
The MPC5534 does not support arbitration with other masters on the external bus. The MPC5534 must be
the only master on the external bus, or act as a slave-only device.
The complex input/output timer functions of the MPC5534 are performed by an enhanced time processor
unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is
programmed using a high-level programming language.
The less complex timer functions of the MPC5534 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs).
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC) with a 5 V
conversion range. The 324 package has 40-channels; the 208 package has 34 channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing
of eQADC trigger sources and external interrupt signal multiplexing.
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