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| 型号： | MPC5566MZP144 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/66页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 3MB FLASH 416PBGA |
| 标准包装： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z6 |
| 芯体尺寸： | 32-位 |
| 速度： | 144MHz |
| 连通性： | CAN，EBI/EMI，以太网，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 256 |
| 程序存储器容量： | 3MB（3M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 128K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 416-BBGA |
| 包装： | 托盘 |
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MPC5566 Microcontroller Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
10
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current
consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the
9
Absolute value of slew rate on power supply pins
—
50
V/ms
10
Required gain at Tj:
– 40o C
BETA 10
60
—
25o C
65
——
150o C
85
500
—
1 The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
3 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
4 It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
5 At peak current for device.
6 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1
). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal)
bulk capacitor (greater than 4
F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01
F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals.
7 IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
8 Refer to Table 1 for the maximum operating frequency.
9 Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
10 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (IDD IVRCCTL).
Table 6. VRC and POR Electrical Specifications (continued)
Spec
Characteristic
Symbol
Min.
Max.
Units
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