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参数资料
| 型号： | MPC5566MZP144 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 60/66页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 3MB FLASH 416PBGA |
| 标准包装： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z6 |
| 芯体尺寸： | 32-位 |
| 速度： | 144MHz |
| 连通性： | CAN，EBI/EMI，以太网，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 256 |
| 程序存储器容量： | 3MB（3M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 128K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 416-BBGA |
| 包装： | 托盘 |
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Revision History for the MPC5566 Data Sheet
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
63
Table 15, Flash EEPROM Module Life:
Replaced (Full Temperature Range) with (TA = TL – TH) in the table title.
Spec 1b, Min. column value changed from 10,000 to 1,000.
Table 16, FLASH BIU Settings vs. Frequency of Operations:
‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
the same row in this table.’
Added fourth row ‘147 MHz’ after the ‘135 MHz’ row and before the ‘Default setting after reset’:
Columns DPFEN, IPFEN, PFLIM, and BFEN are the same as the 135 MHz column.
New values for the following columns: APC = 0b011, RWSC = 0b100, WWSC = 0b01.
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Changed footnotes 1, 5, and 6 to become footnotes 5, 6, and 7. Added footnote 8.
-- footnote 5 82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
-- footnote 6 102 MHz parts allow for 100 MHz system clock + 2% FM.
-- footnote 7 135 MHz parts allow for 132 MHz system clock + 2% FM.
-- footnote 8 147 MHz parts allow for 144 MHz system clock + 2% FM.
Footnote 9: added to the end of the 1st column for the 147 MHz row that reads:
Preliminary setting. Final setting pending characterization.
Footnote 1, deleted ‘FSYS = 132 MHz.’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 19, Reset and Configuration Pin Timing:
Footnote 1, deleted ‘FSYS = 132 MHz.’
Table 20, JTAG Pin AC Electrical Characteristics:
Footnote 1, deleted: ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’
Footnote 1, changed ‘functional’ to ‘Nexus.’
Table 21, Nexus Debug Port Timing.
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location
Description of Changes
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