参数资料
型号: MPC5604PEF0MLL4
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100
文件页数: 68/99页
文件大小: 1130K
代理商: MPC5604PEF0MLL4
MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
70
3.15
Flash memory electrical characteristics
GE
CC T Gain error
±1
LSB
TUE
CC P Total unadjusted error without current
injection
—–2.5
2.5
LSB
TUE
CC T Total unadjusted error with current
injection
—–3
3
LSB
1 V
DD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage
from VSS_HV_ADCx to VDD_HV_ADCx.
2 AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3 When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
5 This parameter includes the sample time t
ADC_S.
6 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
7 See Figure 15.
Table 31. Program and erase specifications
Symbol
C
Parameter
Value
Unit
Min
Typical1
1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
Initial
max2
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
Max3
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
Tdwprogram
P Double Word (64 bits) Program Time4
4 Actual hardware programming times. This does not include software overhead.
22
50
500
s
TBKPRG
P Bank Program (512 KB)4, 5
5 Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
1.45
1.65
33
s
P Bank Program (64 KB)4, 5
0.18
0.21
4.10
s
T16kpperase
P 16 KB Block Pre-program and Erase Time
300
500
5000
ms
T32kpperase
P 32 KB Block Pre-program and Erase Time
400
600
5000
ms
T128kpperase
P 128 KB Block Pre-program and Erase Time
800
1300
7500
ms
Table 30. ADC conversion characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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