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参数资料
| 型号： | MPC5604PEF0VLL4R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100 |
| 文件页数： | 10/99页 |
| 文件大小： | 1130K |
| 代理商： | MPC5604PEF0VLL4R |
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MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
18
— ADC state machine managing 3 request flows: regular command, hardware injected command, software injected
command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
CTU control mode features
— Triggered mode only
— 4 independent result queues (2 × 16 entries, 2 × 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit part
— DMA compatible interfaces
1.5.28
Cross triggering unit (CTU)
The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU
load during the PWM period and with minimized CPU load for dynamic configuration.
It implements the following features:
Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers
Trigger generation unit configurable in sequential mode or in triggered mode
Each Trigger can be appropriately delayed to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger has the capability to generate consecutive commands
ADC conversion command allows to control ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
1.5.29
Nexus development interface (NDI)
The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5604P Power
Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces
to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.
The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal
registers during run time.
The Nexus Interface provides the following features:
Configured via the IEEE 1149.1
All Nexus port pins operate at VDDIO (no dedicated power supply)
Nexus 2+ features supported
— Static debug
— Watchpoint messaging
— Ownership trace messaging
— Program trace messaging
— Real time read/write of any internally memory mapped resources through JTAG pins
— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of
information
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5604PEF0VLL7R | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| MPC5604PEF0VLQ7R | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| MPC5604PEFMLL | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| MPC5604PEFMLQ | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
| MPC5604PFF0MLL7R | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:microcontroller units (MCUs) |
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