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| 型号： | MPC5604PEF0VLL4R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100 |
| 文件页数： | 51/99页 |
| 文件大小： | 1130K |
| 代理商： | MPC5604PEF0VLL4R |
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MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
55
3.10.3
DC electrical characteristics (3.3 V)
Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V] = 1); see
Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol
C
Parameter
Conditions
Value
Unit
Typ
Max
IDD_LV_CORx
T
Sup
p
ly
current
RUN—Maximum mode1
1 Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O
supply current excluded.
VDD_LV_CORx
externally forced at 1.3 V
40 MHz
62
77
mA
64 MHz
71
88
RUN—Typical mode2
2 Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
40 MHz
45
56
64 MHz
52
65
P
RUN—Maximum mode3
3 Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum
frequency, all peripherals enabled.
VDD_LV_CORx
externally forced at 1.3 V
64 MHz
60
75
HALT mode4
4 Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
VDD_LV_CORx
externally forced at 1.3 V
—1.5
10
STOP mode5
5 STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories
OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
VDD_LV_CORx
externally forced at 1.3 V
—1
10
IDD_FLASH
T
Flash during read
VDD_HV_FL at 5.0 V
—
10
12
Flash during erase operation on 1
flash module
VDD_HV_FL at 5.0 V
—
15
19
IDD_ADC
T
ADC—Maximum mode1
VDD_HV_ADC0 at 5.0 V
VDD_HV_ADC1 at 5.0 V
fADC = 16 MHz
ADC_1
3.5
5
ADC_0
3
4
ADC—Typical mode2
ADC_1
0.8
1
ADC_0
0.005 0.006
IDD_OSC
T
Oscillator
VDD_OSC at 5.0 V
8 MHz
2.6
3.2
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)1
Symbol C
Parameter
Conditions
Value
Unit
Min
Max
VIL
D Low level input voltage
—
–0.12
—V
P—
—
0.35 VDD_HV_IOx
V
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