
Clocks and Power Control
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-9
the input source to the SPLL (main system oscillator or EXTCLK). MODCK1, MODCK2, and MODCK3
together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to remain
unchanged in power-down low-power mode, the MODCK signals should not be sampled at wake-up from
this mode. In this case the PORESET pin should remain negated and HRESET should be asserted during
the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator is selected as the input to the SPLL. When
MODCK1 is asserted, the external clock input (EXTCLK pin) is selected as the input to the SPLL. In all
cases, the system clock frequency (freqgclk2) can be reduced by the DFNH[0:2] bits in the SCCR. Note
that freqgclk2(max) occurs when the DFNH bits are cleared.
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or GCLK2. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and MODCK3
values are not affected. They remain the same as they were defined during the most recent power-on reset.
Table 8-1 shows the clock configuration modes during power-on reset (PORESET asserted).
NOTE
The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used
as interrupts, the interrupt source should be removed during PORESET to
insure the MODCK pins are in the correct state on the rising edge of
PORESET.
Table 8-1. Reset Clocks Source Configuration
MODCK[1:3]1
Default Values after
PORESET
SPLL Options
LME
RTSEL
RTDIV
MF + 1
PITCLK
Division
TMBCLK
Division
000
0
1
4
Used for testing purposes.
001
0
1
256
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode disabled.
010
1
0
1
5
256
4
Normal operation, PLL enabled.
Main timing reference is crystal
osc (4 MHz).
Limp mode enabled.
011
1
0
1
256
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode enabled.