
PRELIMINAR
Y
PID9q-604e Hardware Specifications
25
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
1.8.6.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 14, the intrinsic conduction thermal resistance
paths are as follows:
The die junction-to-case thermal resistance
The die junction-to-lead thermal resistance
Figure 13 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
Figure 13. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat
sink attach material (or thermal interface material), and nally to the heat sink where it is removed by
forced-air convection.
Since the silicon thermal resistance is quite small, for a rst-order analysis, the temperature drop in the
silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective
thermal resistances are the dominant terms. The following section provides a thermal management example
for the 604e using one of the commercially available heat sinks.
Table 14. Package Thermal Resistance
Thermal Metric
CBGA
Junction-to-top of die thermal resistance
0.03 C/W
Junction-to-lead (ball) thermal resistance
2.2 C/W
External Resistance
Internal Resistance
(Note the internal versus external package resistance)
Radiation
Convection
Radiation
Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package